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| XILINX APPLICATIONS XAPP001V:  CPIP16-V2.00                BN-3-16-94 |
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README file for the XC300A Counter CPIP16:
==========================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.


CPIP16
------

This counter is a 16-bit binary up counter with a Clock Enable (CE) and an
asynchronous reset (RST).  It decodes the lower 3 bits of the counter at a
value of 6.  This value is pipelined because it will be sent to the upper
bits of the counter as a parallel enable along with the CE input.  In the
low-level, symbol this pipelined enable is called CEO.  The counter is broken
up into 3 bit sections as described in the application note in the Data Book.
CEO is pipelined to achieve speeds of 70 MHz in the XC3000A-6 and 107 MHz in 
the XC3100A.3.  Because a high-level schematic was used, the CLB and net names 
have the prefix CPIPA/ in front of them.  The .LCA file contains hand 
placement and routing to illustrate the preferred organization in the FPGA.

Design files included in directory CPIP16:

  README          This README file
  SCH\CPIP16H.1   Top-level Viewlogic V4.1.3a schematic
  SCH\CPIP16.1    16-Bit Up counter with Pipelined TC (CEO) (Sheet 1)
  SYM\CPIP16.1    Viewlogic Symbol for Counter
  SYM\*.1         Viewlogic Symbols
  WIR\*.1         Viewlogic wire file

  XNF\            Xilinx Netlists for High Level Schematic
  CPIP16H.LCA     Placed and Routed LCA file
  CPIP16H.CST     Contraints file for the CLB placement.
  CPIP16H.XRP     Xdelay timing report using XC3000A-6

Software Versions used:
  DS390 Version 4.1.3a Viewlogic and Interface

Recommended Layout, Routing:

  The recommended layout is shown below and is in the constraints file
CPIP16H.CST.  The placement generally goes from LSB to MSB down the first 
column.  CLB Q2 has been placed to make the CPIPA/CEO (pipelined parallel 
enable) from CLB Q2 have the shortest routing to the vertical long line.


;Sample Placement Constraints File:
place block Q15 : BA;
place block Q5 : DA;
place block Q6 : EA;
place block Q8 : FA;
place block CPIPA/CEO8 : GA;
place block Q9 : HA;

place block Q0 : AB;
place block Q2 : BB;
place block Q3 : CB;
place block CPIPA/CEO14 : DB;
place block Q14 : EB;
place block Q12 : FB;
place block CPIPA/CEO11 : GB;
place block Q11 : HB;


  Now hand routing of the CPIPA/CEO longline has to be done. Recommended 
routing is to first route the CPIPA/CEO signal on the vertical longlines 
to the .A inputs of most of the CLBs.  The routing has been carefully 
done to select best method for jumping onto the vertical longline needed 
for the column of CLBs.  Similarly the CE input from the PAD has been routed 
in the best way to get onto the vertical long line for the .EC inputs.  

Performance:

   To analyze the performance using stand-alone XDELAY, only clock-to-set-up 
paths starting at flip-flops Q0, Q1, Q2 and CPIPA/CEO need be considered.
All other paths have 8 clock periods in which to settle.
