XMAKE Version pre5.0.0m
Copyright (c) 1989-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

XMAKE: Generating makefile 'calc.mak'...
XMAKE: Profile used is 'n:\data\xdm.pro'.

XMAKE: Execute command 'wir2xnf -B -OD xnf calc calc.xnf'.
******************************************************************************
WIR2XNF Version Pre 5.0.0l
(c) Copyright 1988-1994 Xilinx Inc.  All rights reserved.
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.


Input project     : calc
Output XNF file   : calc.xnf
Output CRS file   : calc.crs
Output error file : calc.err
B option          : ON
C option          : OFF
X option          : OFF
F option          : OFF
Parttype          : Unspecified on command line
Sub directory     : xnf

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:CALC.1 ...
0 error(s) and 0 warning(s) in project primary:CALC.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:STACK.1 ...
0 error(s) and 0 warning(s) in project primary:STACK.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:7SEGDEC.1 ...
0 error(s) and 0 warning(s) in project primary:7SEGDEC.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:DEBOUNCE.1 ...
0 error(s) and 0 warning(s) in project primary:DEBOUNCE.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:OSC_3K.1 ...
0 error(s) and 0 warning(s) in project primary:OSC_3K.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:SW7.1 ...
0 error(s) and 0 warning(s) in project primary:SW7.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:ALU.1 ...
0 error(s) and 0 warning(s) in project primary:ALU.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:ANDBLK2.1 ...
0 error(s) and 0 warning(s) in project primary:ANDBLK2.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:ORBLK2.1 ...
0 error(s) and 0 warning(s) in project primary:ORBLK2.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:XORBLK2.1 ...
0 error(s) and 0 warning(s) in project primary:XORBLK2.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:MUXBLK5.1 ...
0 error(s) and 0 warning(s) in project primary:MUXBLK5.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:MUXBLK2.1 ...
0 error(s) and 0 warning(s) in project primary:MUXBLK2.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:CONTROL.1 ...
0 error(s) and 0 warning(s) in project primary:CONTROL.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:STATMACH.1 ...
0 error(s) and 0 warning(s) in project primary:STATMACH.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:7SEG_TRU.1 ...
0 error(s) and 0 warning(s) in project primary:7SEG_TRU.1.

CHECK - V4.09; Workview 4.1.3a 081092, 3000 Series
c Copyright 1985,1992 by Viewlogic Systems, Inc.
Checking primary:LED_TRU.1 ...
0 error(s) and 0 warning(s) in project primary:LED_TRU.1.
Components written to file xnf\m2_1e.xnf.                                       
Components written to file xnf\m2_1.xnf.                                       
Components written to file xnf\m4_1e.xnf.                                       
Components written to file xnf\muxblk5.xnf.                                       
Components written to file xnf\andblk2.xnf.                                       
Components written to file xnf\fd4ce.xnf.                                       
Components written to file xnf\adsu4.xnf.                                       
Components written to file xnf\xorblk2.xnf.                                       
Components written to file xnf\orblk2.xnf.                                       
Components written to file xnf\muxblk2.xnf.                                       
Components written to file xnf\alu.xnf.                                       
Components written to file xnf\7segdec.xnf.                                       
Components written to file xnf\d2_4e.xnf.                                       
Components written to file xnf\fd.xnf.                                       
Components written to file xnf\fdre.xnf.                                       
Components written to file xnf\fd4re.xnf.                                       
Components written to file xnf\stack.xnf.                                       
Components written to file xnf\7seg_tru.xnf.                                       
Components written to file xnf\m2_1b1.xnf.                                       
Components written to file xnf\ftcle.xnf.                                       
Components written to file xnf\cb2cled.xnf.                                       
Components written to file xnf\statmach.xnf.                                       
Components written to file xnf\control.xnf.                                       
Components written to file xnf\led_tru.xnf.                                       
Components written to file xnf\sw7.xnf.                                       
Components written to file xnf\debounce.xnf.                                       
Components written to file xnf\ftce.xnf.                                       
Components written to file xnf\cb4ce.xnf.                                       
Components written to file xnf\osc_3k.xnf.                                       
Components written to file xnf\calc.xnf.                                       
0 Errors and 0 Warnings occurred during processing.

XMAKE: Set the part type to '3020PC68-50' from 'xnf\calc.xnf'.
XMAKE: Running with the following XMAKE options: (none)
XMAKE: Makefile saved in 'calc.mak'.

XMAKE: Making 'calc.bit'...

XMAKE: Execute command 'xnfmerge -A -D xnf -D . -P 3020PC68-50 xnf\calc.xnf calc.xff'.
******************************************************************************
XNFMERGE Ver. pre-5.0.0r
(c) Copyright 1987-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.


List of files read
    Read file xnf\calc.xnf
    Read file xnf\osc_3k.xnf
    Read file xnf\cb4ce.xnf
    Read file xnf\ftce.xnf
    Read file xnf\debounce.xnf
    Read file xnf\fd.xnf
    Read file xnf\sw7.xnf
    Read file xnf\led_tru.xnf
    Read file xnf\control.xnf
    Read file xnf\statmach.xnf
    Read file xnf\m2_1.xnf
    Read file xnf\cb2cled.xnf
    Read file xnf\ftcle.xnf
    Read file xnf\m2_1b1.xnf
    Read file xnf\7seg_tru.xnf
    Read file xnf\stack.xnf
    Read file xnf\fd4re.xnf
    Read file xnf\fdre.xnf
    Read file xnf\m4_1e.xnf
    Read file xnf\m2_1e.xnf
    Read file xnf\d2_4e.xnf
    Read file xnf\7segdec.xnf
    Read file xnf\alu.xnf
    Read file xnf\muxblk2.xnf
    Read file xnf\orblk2.xnf
    Read file xnf\xorblk2.xnf
    Read file xnf\adsu4.xnf
    Read file xnf\fd4ce.xnf
    Read file xnf\andblk2.xnf
    Read file xnf\muxblk5.xnf
Netlist written to file calc.xff

XMAKE: Execute command 'xnfprep calc.xff calc.xtf parttype=3020PC68-50'.
******************************************************************************
xnfprep [pre5.0.0w]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

+ xnfprep  @ 1994/03/06 13:53:55 [00:00:43]
  
  + Parameters 
    ----------------------- 
    design          = calc.xff 
    outfile         = calc.xtf 
    report          = *** 
    savesig         = FALSE 
    parttype        = 3020PC68-50 
    cstfile         = *** 
    logfile         = xnfprep.log 
    ----------------------- 
  
  xnfprep:  running design rule checker ...
  
  
  xnfprep:  trimming unnecessary and redundant logic...
  
  
  xnfprep:  running design rule checker on trimmed design...
  
  
  XNFPREP SUMMARY 
  ---------------
  0 Errors found
  2 Warnings found
  5 Unnecessary inverters and buffers removed
  20 Unnecessary or disabled symbols removed
  17 Sourceless or loadless signals removed
  
  Refer to the calc.prp file for details.
  
  Output netlist written to file calc.xtf.
  
  
- xnfprep  @ 1994/03/06 13:54:43 [00:01:31]
= -------- @ 1994/03/06 00:00:48 [00:00:48]

+ xnfprep required [1356.694] Kbytes of dynamic/allocated memory 

+ Data Manager Auto Save 
  Saving MAP_XNF_TRIM cell "calc" 
- Data Manager Auto Save 

XMAKE: Execute command 'xnfmap -P 3020PC68-50 calc.xtf calc.map'.
******************************************************************************
XNFMAP Ver. pre-5.0.0r
(c) Copyright 1987-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.
Reading file calc.xtf...

Checking network for logical errors...

Preparing design...

Assigning logic to LCA elements...

Preparing GUIDE file...

Checking mapped logic blocks...

DESIGN SUMMARY:
	Part type=3020PC68-50
	52 of 64 CLBs used
	23 of 58 I/O pins used
	0 of 6 internal IOBs used
	0 of 16 internal three-state signals used (0 TBUFS used)

	33  CLB flipflops used

	Total number of WARNINGS generated during mapping = 0.
	Total number of ERRORS generated during mapping = 0.

Writing design file calc.map...

Writing guide file calc.pgf...

XMAKE: Execute command 'map2lca -P 3020PC68-50 calc.map calc.lca'.
******************************************************************************
MAP2LCA Ver. pre-5.0.0r
(c) Copyright 1988-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

Checking network for logical errors...
Assigning logic to LCA elements...


SUMMARY: Part type=3020PC68-50
         52 of 64 CLBs used
         23 of 58 I/O pins used
         0 of 6 internal IOBs used
         0 of 16 internal three-state signals used
Design written to file calc.lca (APR constraints in calc.scp)

XMAKE: Execute command 'apr -W -Y calc.lca calc.lca'.
******************************************************************************
AUTOMATIC PLACE AND ROUTE PROGRAM -- Version pre-5.0.0r
Copyright (C) 1986-1994 by Xilinx, Inc.  All Rights Reserved.
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.
Sun Mar  6 13:55:15 1994
 Input Design File: calc.lca
         Part Type: 3020PC68
       Speed Grade: -50
 Guide Design File: (none)
    Schematic File: calc.scp
  Constraints File: (none)
           Options: -a3 -r4 -s24771 -w -y
Output Design File: calc.lca
       Report File: calc.rpt
      Message File: (none)
Reading input design...
Reading constraints...
Placing blocks...

Initial score: *64198*

Annealing...
Estimated execution time for placement: 00:00:00
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
   36972.1  ****   49906   78%   60524  *****   6.6%    00:00:00
   35374.1   -4%   49906   78%   61974   2.4%   6.2%    00:00:01
   32565.5   -8%   49906   78%   61486  -0.8%   5.1%    00:00:01
   28731.9  -12%   49906   78%   61079  -0.7%   5.1%    00:00:02
   24316.4  -15%   49906   78%   62861   2.9%   4.7%    00:00:03
   19762.0  -19%   49906   78%   63393   0.8%   6.2%    00:00:03
   15239.1  -23%   49906   78%   60846  -4.0%   5.3%    00:00:04
   11146.4  -27%   49906   78%   59468  -2.3%   5.7%    00:00:05
    7999.7  -28%   49906   78%   61242   3.0%   6.8%    00:00:06
    5629.2  -30%   49906   78%   60010  -2.0%   5.6%    00:00:07
    3955.5  -30%   49699   77%   59907  -0.2%   6.2%    00:00:08
    2717.9  -31%   49320   77%   58813  -1.8%   5.5%    00:00:09
    2003.3  -26%   46054   72%   55145  -6.2%   6.5%    00:00:11
    1482.1  -26%   43644   68%   53672  -2.7%   6.4%    00:00:12
    1146.9  -23%   43644   68%   53025  -1.2%   6.6%    00:00:13
     895.1  -22%   43644   68%   52101  -1.7%   5.4%    00:00:15
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
     739.3  -17%   40303   63%   47529  -8.8%   7.4%    00:00:16
     613.2  -17%   39779   62%   44993  -5.3%   5.0%    00:00:18
     534.5  -13%   35491   55%   41017  -8.8%   5.8%    00:00:19
     475.5  -11%   35491   55%   40012  -2.4%   5.0%    00:00:21
     415.0  -13%   33446   52%   39818  -0.5%   7.5%    00:00:23
     379.4   -9%   28553   44%   34286 -13.9%   6.6%    00:00:25
     352.3   -7%   27539   43%   33453  -2.4%   8.0%    00:00:26
     298.7  -15%   26960   42%   30614  -8.5%   5.1%    00:00:28
     252.4  -15%   25050   39%   30434  -0.6%   6.6%    00:00:30
     233.2   -8%   25050   39%   28800  -5.4%   3.7%    00:00:32
     217.3   -7%   24777   39%   27788  -3.5%   3.9%    00:00:35
     184.7  -15%   23789   37%   26358  -5.1%   5.3%    00:00:37
     162.7  -12%   22807   36%   24985  -5.2%   4.1%    00:00:39
     152.0   -7%   21603   34%   23682  -5.2%   4.6%    00:00:42
     135.1  -11%   21140   33%   23815   0.6%   5.6%    00:00:44
     134.8   -0%   21140   33%   23539  -1.2%   2.6%    00:00:47
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
     141.1    5%   21026   33%   22948  -2.5%   3.4%    00:00:49
     138.3   -2%   20121   31%   22097  -3.7%   4.1%    00:00:52
     127.2   -8%   20121   31%   22280   0.8%   4.4%    00:00:55
     112.1  -12%   19764   31%   21731  -2.5%   3.6%    00:00:57
     102.6   -9%   19290   30%   20932  -3.7%   3.4%    00:01:00
      86.6  -16%   19218   30%   20335  -2.9%   3.0%    00:01:03
      77.6  -10%   18712   29%   19414  -4.5%   1.7%    00:01:06
      68.6  -12%   18161   28%   19033  -2.0%   2.2%    00:01:09
      60.0  -13%   17913   28%   18497  -2.8%   1.6%    00:01:12
      54.4   -9%   17626   27%   18302  -1.1%   1.5%    00:01:15
      50.4   -7%   17626   27%   18151  -0.8%   1.3%    00:01:18
      43.8  -13%   17626   27%   18088  -0.3%   0.9%    00:01:21
      39.8   -9%   17516   27%   17954  -0.7%   1.0%    00:01:25
      36.0   -9%   17479   27%   17758  -1.1%   0.8%    00:01:28
      33.0   -9%   17287   27%   17601  -0.9%   0.8%    00:01:32
      28.6  -13%   17015   27%   17324  -1.6%   0.9%    00:01:35
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
      26.3   -8%   17015   27%   17289  -0.2%   0.7%    00:01:39
      23.6  -10%   17015   27%   17220  -0.4%   0.6%    00:01:42
Quenching...
       0.0  ****   16985   26%   16987  -1.4%   0.0%    00:01:46
       0.0  ****   16985   26%   16985  -0.0%   0.0%    00:01:49
       0.0  ****   16985   26%   16985   0.0%   0.0%    00:01:53

Final score: *16985*

Total Placement CPU time: 00:01:53

Adopting new placement...
Writing placed but unrouted design...
Assigning long lines...
Routing nets...

	Iteration 1...
	Using delay-driven detail router...
	Detail Routing (with Rip-up & Retry Routing)...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	Rip-up & Retry Routing and Routing Improvement
	on 0 unrouted load pins in unwritten design...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.
	Routing CPU time: 00:00:23
	Writing new design...

	Placement Improvement...
	Using delay-driven detail router...
	Percent blks scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.
	Routing CPU time: 00:00:57
	Writing new design...

	Timing Improvement...
	Using delay-driven detail router...
	Exhaustive Rip-up Retry...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.

Total Routing CPU time: 00:03:08

Checking results...
Timing nets...
Writing report...
Writing new design...

Total elapsed time: 0 hrs, 5 mins, 15 secs

There are 0 unrouted load pins.
Done.
Sun Mar  6 14:00:29 1994

XMAKE: Execute command 'makebits -S0 -R2 -XB -YA calc.lca'.
******************************************************************************
Xilinx LCA MAKEBITS Ver. 4.8.0
Copyright 1985-1994 Xilinx Inc.  All Rights Reserved.
makebits: Making bitstream..
Loading die/package file...
Loading design file...


Timing nets...

Xilinx LCA MAKEBITS Ver. 4.8.0 ended normally

XMAKE: 'calc.bit' has been made.
