ppr [pre-5.0.0o]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

*** Warning [EXPIRE:WARNING]
    This version of the ppr program has a built-in expiration date.  
    It will stop running 66 days from today.



+ ppr  @ 1994/03/06 13:25:26 [00:00:38]
  
  + Parameters 
    ----------------------- 
    design            = calc.map 
    outfile           = <design name> 
    parttype          = 3020APC68-7 
    estimate          = FALSE 
    logfile           = ppr.log 
    ----------------------- 
  
  + Additional Specified or Non-Default Parameters 
    ----------------------- 
    seed              = 762960326 
    ----------------------- 
    
    Parameter values from the xactinit.dat files
    [Environment Variable XACT = j:\;k:\;o:\;l:\;n:\]
    --------------------------------------------
    no xactinit.dat parameter values defined
    --------------------------------------------
    
  
  ppr:  Reading input design data...
  
  
  + xnfmxn2  @ 1994/03/06 13:25:30 [00:00:42]
  - xnfmxn2  @ 1994/03/06 13:26:07 [00:01:19]
  = -------- @ 1994/03/06 00:00:37 [00:00:37]
  
  + picprep  @ 1994/03/06 13:26:07 [00:01:19]
  - picprep  @ 1994/03/06 13:26:12 [00:01:24]
  = -------- @ 1994/03/06 00:00:05 [00:00:05]
  Speedfile version 3000A.1, revision 3020A.4.
  
  
  + cstmerge  @ 1994/03/06 13:26:17 [00:01:29]
    
    + Loading the PIC net list  @ 13:26:17 [00:01:29]
    - Loading the PIC net list  @ 13:26:17 [00:01:29]
    = ------------------------- @ 00:00:00 [00:00:00]
    
    + CSTMerge main routines  @ 13:26:17 [00:01:29]
    - CSTMerge main routines  @ 13:26:23 [00:01:35]
    = ----------------------- @ 00:00:06 [00:00:06]
    
    + Writing PIC net list  @ 13:26:23 [00:01:35]
    - Writing PIC net list  @ 13:26:23 [00:01:35]
    = --------------------- @ 00:00:00 [00:00:00]
  - cstmerge  @ 1994/03/06 13:26:23 [00:01:35]
  = --------- @ 1994/03/06 00:00:06 [00:00:06]
  
  ppr:  Placing logic...
  
  
  + placer  @ 1994/03/06 13:26:25 [00:01:37]

    *** PPR: WARNING 6811: 
          This design has 1 purely combinational loop.  Such loops should be
          avoided.  If at all possible, please modify the design to eliminate 
          all unclocked feedback paths. 
          
          To permit path analysis during design implementation, all loops will
          be broken by cutting out the last source-to-load connection. A
          consequence is that the analyzer will not account for ANY paths
          through that connection.  This may cause the final performance of
          your design to be sub-optimal. 
          
          You can instruct the path analyzer to cut out connections of your
          choice, by using timespec "ignore" attributes.  For details, consult
          the PPR documentation. 
    A loop of 1 source-to-load connections: 
      FG4 FG_OSC_3K/Q          (Net OSC_3K/Q) to 
    first gate again.
    

    *** PPR: WARNING 7035: 
          To suppress the listing of paths for categories with no timing 
          specifications, set PPR parameter tsi_show_all=FALSE. 
    
    + Loading the tif model  @ 13:26:31 [00:01:43]
    - Loading the tif model  @ 13:26:31 [00:01:43]
    = ---------------------- @ 00:00:00 [00:00:00]
    
    + Getting delays as a function of delta_x and
    + delta_y                                     @ 13:26:32 [00:01:44]
      
      + dly_tab  @ 1994/03/06 13:26:32 [00:01:44]
      - dly_tab  @ 1994/03/06 13:26:34 [00:01:46]
      = -------- @ 1994/03/06 00:00:02 [00:00:02]
      
      + dly_tab  @ 1994/03/06 13:26:34 [00:01:46]
      - dly_tab  @ 1994/03/06 13:26:35 [00:01:47]
      = -------- @ 1994/03/06 00:00:01 [00:00:01]
    - Getting delays as a function of delta_x and
    - delta_y                                     @ 13:26:36 [00:01:48]
    = ------------------------------------------- @ 00:00:04 [00:00:04]
    
    + dly_tab  @ 1994/03/06 13:26:36 [00:01:48]
    - dly_tab  @ 1994/03/06 13:26:36 [00:01:48]
    = -------- @ 1994/03/06 00:00:00 [00:00:00]
    
       Score    @   Time 
    
        8596  ....  00:01:59 
    
        8523  ....  00:02:00 
    
        8523  ....  00:02:02 
    
        8395  ....  00:02:03 
    
        8150  ....  00:02:07 
    
        7290  ....  00:02:11 
    
        7100  ....  00:02:14 
    
        6569  ....  00:02:18 
    
        5973  ....  00:02:23 
    
        5973  ....  00:02:27 
    
        5721  ....  00:02:31 
    
        4946  ....  00:02:36 
    
        4946  ....  00:02:40 
    
        4946  ....  00:02:44 
    
        4946  ....  00:02:49 
    
        4940  ....  00:02:53 
    
        4666  ....  00:02:57 
    
        4509  ....  00:03:01 
    
        4452  ....  00:03:06 
    
        4251  ....  00:03:10 
    
        4164  ....  00:03:14 
  - placer  @ 1994/03/06 13:29:34 [00:04:46]
  = ------- @ 1994/03/06 00:03:09 [00:03:09]
  
  ppr:  Routing signals...
  
  
  + router  @ 1994/03/06 13:29:35 [00:04:47]
    Begin pre-routing, Phase 1, TIMING=OFF; 36 connections. 
    Begin pre-routing, Phase 2, TIMING=OFF; 10 connections. 
    Begin pre-routing, Phase 3, TIMING=OFF; 229 connections. 
    
    + Begin routing, NO_RIP, TIMING=OFF; 238 connections. 
    Begin fixing 6 unroutes on 5 nets, (0 VCC/GND), TIMING=OFF;  
    Begin fixing 1 unroutes on 1 nets, (0 VCC/GND), TIMING=OFF;  
    
    Design has  0  unroutes.
    
  - router  @ 1994/03/06 13:30:30 [00:05:42]
  = ------- @ 1994/03/06 00:00:55 [00:00:55]
  
  ppr:  Generating .LCA File...
  
  
  + pic2lca  @ 1994/03/06 13:30:32 [00:05:44]
    
    + Loading the PIC netlist  @ 13:30:32 [00:05:44]
    - Loading the PIC netlist  @ 13:30:33 [00:05:45]
    = ------------------------ @ 00:00:01 [00:00:01]

    *** PPR: WARNING 10601: 
          The block name 'WE' associated with the instance
          'CONTROL/STATMACH/$1I7/$1I37' has already been used to name another
          block.  Another block name will be created for this block. 

    *** PPR: WARNING 10609: 
          The new block name 'CONTROL/STATMACH/OTHER' is assigned to the
          instance 'CONTROL/STATMACH/$1I7/$1I37'. 
    
    + Loading the tif model  @ 13:30:41 [00:05:53]
    - Loading the tif model  @ 13:30:41 [00:05:53]
    = ---------------------- @ 00:00:00 [00:00:00]
  - pic2lca  @ 1994/03/06 13:30:46 [00:05:58]
  = -------- @ 1994/03/06 00:00:14 [00:00:14]
  
  ppr:  Making Report File...
  
  
  + pprsum  @ 1994/03/06 13:30:48 [00:06:00]
    
    + Cell Data Acquisition  @ 13:30:48 [00:06:00]
    - Cell Data Acquisition  @ 13:30:51 [00:06:03]
    = ---------------------- @ 00:00:03 [00:00:03]
    
    + Summary Report Generation  @ 13:30:51 [00:06:03]
    - Summary Report Generation  @ 13:30:53 [00:06:05]
    = -------------------------- @ 00:00:02 [00:00:02]
  - pprsum  @ 1994/03/06 13:30:53 [00:06:05]
  = ------- @ 1994/03/06 00:00:05 [00:00:05]
  Wrote report on the result without delay optimization to calc.rpf. 
  
  ppr:  Routing signals...
  
  
  + router  @ 1994/03/06 13:30:53 [00:06:05]
    
    + Loading the tif model  @ 13:30:54 [00:06:06]
    - Loading the tif model  @ 13:30:54 [00:06:06]
    = ---------------------- @ 00:00:00 [00:00:00]
    Begin pre-routing, Phase 1, TIMING=PATH; 36 connections. 
    Begin pre-routing, Phase 2, TIMING=PATH; 10 connections. 
    Begin pre-routing, Phase 3, TIMING=PATH; 229 connections. 
    
    + Begin routing, NO_RIP, TIMING=PATH; 238 connections. 
    Begin fixing 9 unroutes on 8 nets, (0 VCC/GND), TIMING=PATH; (First LCA
    made) 
    Begin fixing 3 unroutes on 3 nets, (0 VCC/GND), TIMING=PATH; (First LCA
    made) 
    Improving a   76.4ns  path with 9 pins. 
    Improving a   75.6ns  path with 9 pins. 
    
    Design has  0  unroutes.
    
    ----------------------------------------------------------------------
    Timing analysis summary
    ----------------------------------------------------------------------
    
        Deadline  Actual(*)  Specification
        --------  ---------  ------------- 
          <auto>   75.6ns    DEFAULT_FROM_FFS_TO_FFS=FROM:ffs:TO:ffs 
          <auto>   25.0ns    DEFAULT_FROM_PADS_TO_FFS=FROM:pads:TO:ffs 
          <auto>   53.4ns    DEFAULT_FROM_FFS_TO_PADS=FROM:ffs:TO:pads 
    (*) Note: please run xdelay to confirm the actual path delays computed by
    PPR. 

    *** PPR: WARNING 7028: 
          The design has flip-flops with asynchronous set/reset controls
          (PRE/SD or CLR/RD pins).  When PPR analyzes design timing, it does
          not trace paths through the asynchronous set/reset input and on
          through the Q output.
          
          If you want PPR to control the delay on paths through asynchronous
          set/reset pins, you must split the delay requirement into two
          segments: one ending at the set/reset input, and the other beginning
          at the flip-flop output.
          If you want PPR not to analyze paths that lead to asynchronous
          set/reset pins, attach an IGNORE specification to the pin(s) or
          signal(s).
          
          By default, XDelay reports all paths through asynchronous set/reset
          pins. To prevent XDelay from showing these paths, use FlagBlk
          CLB_Disable_SR_Q on the appropriate flip-flops. 
  - router  @ 1994/03/06 13:33:40 [00:08:52]
  = ------- @ 1994/03/06 00:02:47 [00:02:47]
  
  ppr:  Generating .LCA File...
  
  
  + pic2lca  @ 1994/03/06 13:33:41 [00:08:53]
    
    + Loading the PIC netlist  @ 13:33:41 [00:08:53]
    - Loading the PIC netlist  @ 13:33:43 [00:08:55]
    = ------------------------ @ 00:00:02 [00:00:02]

    *** PPR: WARNING 10604: 
          A .LCA file already exists.  The old .LCA file will be saved as
          'calc.lcb'. 
    
    + Loading the tif model  @ 13:33:51 [00:09:03]
    - Loading the tif model  @ 13:33:51 [00:09:03]
    = ---------------------- @ 00:00:00 [00:00:00]
  - pic2lca  @ 1994/03/06 13:33:56 [00:09:08]
  = -------- @ 1994/03/06 00:00:15 [00:00:15]
  
  ppr:  Making Report File...
  
  
  + pprsum  @ 1994/03/06 13:33:58 [00:09:10]
    
    + Cell Data Acquisition  @ 13:33:58 [00:09:10]
    - Cell Data Acquisition  @ 13:33:58 [00:09:10]
    = ---------------------- @ 00:00:00 [00:00:00]
    
    + Summary Report Generation  @ 13:33:58 [00:09:10]
    - Summary Report Generation  @ 13:34:00 [00:09:12]
    = -------------------------- @ 00:00:02 [00:00:02]
  - pprsum  @ 1994/03/06 13:34:00 [00:09:12]
  = ------- @ 1994/03/06 00:00:02 [00:00:02]
- ppr  @ 1994/03/06 13:34:00 [00:09:12]
= ---- @ 1994/03/06 00:08:34 [00:08:34]

+ ppr required [3849.381] Kbytes of dynamic/allocated memory 
