XMAKE Version pre5.0.0n
Copyright (c) 1989-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

XMAKE: Generating makefile 'calc.mak'...
XMAKE: Profile used is the current XDM settings.
XMAKE: Making 'xnf\calc.xnf' because it does not exist.

XMAKE: Execute command 'annotate calc.sch '.
******************************************************************************
Annotation
"OrCAD/SDT 386+ v1.10    03-SEP-93"
(C)Copyright 1991,1992,1993 OrCAD, Inc. ALL RIGHTS RESERVED.
Reading Configuration Data File: sdt.bcf
Initial memory allocation: 2000K.
Reading Library: j:\xc4000\XC4000.LIB
Reading Library: j:\xc4000\XC4000O.LIB
Reading Library: j:\xc4000\XBLOX.LIB
Opening "calc.sch"
Opening "OSC_4K.sch"
Opening "LED_INV.sch"
Opening "DEBOUNCE.sch"
Opening "7SEG_INV.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATE_4K.sch"
Opening "STACK_4K.sch"
Opening "calc.sch"
Opening "calc.sch"
Opening "OSC_4K.sch"
Opening "LED_INV.sch"
Opening "DEBOUNCE.sch"
Opening "7SEG_INV.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATE_4K.sch"
Opening "STACK_4K.sch"
Annotating "calc.sch"
Annotating "OSC_4K.sch"
Annotating "LED_INV.sch"
Annotating "DEBOUNCE.sch"
Annotating "7SEG_INV.sch"
Annotating "SW7.sch"
Annotating "ALU.sch"
Annotating "ANDBLK2.sch"
Annotating "ORBLK2.sch"
Annotating "XORBLK2.sch"
Annotating "MUXBLK5.sch"
Annotating "MUXBLK2.sch"
Annotating "7SEGDEC.sch"
Annotating "CONTROL.sch"
Annotating "STATE_4K.sch"
Annotating "STACK_4K.sch"

XMAKE: Execute command 'inet calc.sch '.
******************************************************************************
Incremental NetList
"OrCAD/SDT 386+ v1.10    03-SEP-93"

(C)Copyright 1991,1992,1993 OrCAD, Inc. ALL RIGHTS RESERVED.
Reading Configuration Data File: sdt.bcf
Initial memory allocation: 2000K.
Reading Library: j:\xc4000\XC4000.LIB
Reading Library: j:\xc4000\XC4000O.LIB
Reading Library: j:\xc4000\XBLOX.LIB
Opening "calc.sch"
Opening "OSC_4K.sch"
Opening "LED_INV.sch"
Opening "DEBOUNCE.sch"
Opening "7SEG_INV.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATE_4K.sch"
Opening "STACK_4K.sch"
Opening "calc.sch"
Opening "OSC_4K.sch"
Opening "LED_INV.sch"
Opening "DEBOUNCE.sch"
Opening "7SEG_INV.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATE_4K.sch"
Opening "STACK_4K.sch"

Opening "calc.sch"
Building Network "calc.sch"


"calc.sch"

***.....*******
Building Network - 54856 Available Nodes.
***********..........***......
..............*..............................
........................................****.
....................................***

Write INF file for : calc.sch


"calc.sch"

***.....................................*...*
*...*.........*...*....*....*....*....*....*.
..*...*...*....*...*....*...*....*...*...*...
*...*...*...*...*.......*...*...*...*...*....
*....*....*....*...*...*...*...*...*...*...**
..

WriteInetList: complete

Opening "OSC_4K.sch"
Building Network "OSC_4K.sch"


"OSC_4K.sch"

**********
Building Network - 54856 Available Nodes.
**************.****.*.***

Write INF file for : OSC_4K.sch


"OSC_4K.sch"

**.*.*...**..*...*..**

WriteInetList: complete

Opening "LED_INV.sch"
Building Network "LED_INV.sch"


"LED_INV.sch"

**********
Building Network - 54856 Available Nodes.
**************....****....*........
***

Write INF file for : LED_INV.sch


"LED_INV.sch"

**....*........*...**............*..*...*...*
..*...*...*..*...*...*..*...*...**

WriteInetList: complete

Opening "DEBOUNCE.sch"
Building Network "DEBOUNCE.sch"


"DEBOUNCE.sch"

**********
Building Network - 54856 Available Nodes.
**************...****...*...***

Write INF file for : DEBOUNCE.sch


"DEBOUNCE.sch"

**...*...*...**.....*....*....*..*...*..*..*.
...**

WriteInetList: complete

Opening "7SEG_INV.sch"
Building Network "7SEG_INV.sch"


"7SEG_INV.sch"

**********
Building Network - 54856 Available Nodes.
**************........****........*
................***

Write INF file for : 7SEG_INV.sch


"7SEG_INV.sch"

**........*................*...**............
............*..*...*...*..*...*...*..*...*...
*..*...*...*..*...*...*..*...*...*..*...*...*
..*...*...**

WriteInetList: complete

Opening "SW7.sch"
Building Network "SW7.sch"


"SW7.sch"

***......*******
Building Network - 54856 Available Nodes.
**************........****...
.....*.......***

Write INF file for : SW7.sch


"SW7.sch"

**........*.......*...**..............*...*..
.*...*...*........*...*...*...*...*...*...*..
.*...*...*...*.......*

WriteInetList: complete

Opening "ALU.sch"
Building Network "ALU.sch"


"ALU.sch"

***...*******
Building Network - 54856 Available Nodes.
*****....******.................
.........***.................................
..........................................*..
.............................................
.............................................
.............................................
.............................................
................***.....................*....
......................***

Write INF file for : ALU.sch


"ALU.sch"

**.....................*.....................
.....*...**.....*.....*......*......*......*.
.....*.......*.......*.......*.......*...*...
*...*...*...*...*...*...*..*...*...*...*...*.
..*...*..*...*...*...*..*...*...*...*...*...*
...*...*...*...*...*...*...*..*..*..*..*..*..
*..*..**

WriteInetList: complete

Opening "ANDBLK2.sch"
Building Network "ANDBLK2.sch"


"ANDBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : ANDBLK2.sch


"ANDBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "ORBLK2.sch"
Building Network "ORBLK2.sch"


"ORBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : ORBLK2.sch


"ORBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "XORBLK2.sch"
Building Network "XORBLK2.sch"


"XORBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : XORBLK2.sch


"XORBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "MUXBLK5.sch"
Building Network "MUXBLK5.sch"


"MUXBLK5.sch"

**********
Building Network - 54856 Available Nodes.
*****..........******..............
.***.........................................
...........*.................................
.............................................
..........................................***
...........................*....***

Write INF file for : MUXBLK5.sch


"MUXBLK5.sch"

**...........................*....*...**.....
....*.....*..*...*..*..*..*..*.....*..*.....*
.....*..*...*..*..*..*..*..*..*...*..*..*..*.
.*..*..*...*..*..*..*..*..**

WriteInetList: complete

Opening "MUXBLK2.sch"
Building Network "MUXBLK2.sch"


"MUXBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************.............****....
.........****

Write INF file for : MUXBLK2.sch


"MUXBLK2.sch"

**.............**...**....*..*..*..*.....*..*
..*..*..*..*..*..*..*..**

WriteInetList: complete

Opening "7SEGDEC.sch"
Building Network "7SEGDEC.sch"


"7SEGDEC.sch"

**********
Building Network - 54856 Available Nodes.
**************.....................
.............................................
..............****...........****

Write INF file for : 7SEGDEC.sch


"7SEGDEC.sch"

**...........**...**.........................
.........*.....................*..*..........
..........*..*.................*.............
......*..*..*..*..*..*..*..*..*..*..*..*..*..
*..*..*..*..*..*..*..*..*..*..*..*..*..*..*..
*..*..*..*..**

WriteInetList: complete

Opening "CONTROL.sch"
Building Network "CONTROL.sch"


"CONTROL.sch"

**********
Building Network - 54856 Available Nodes.
*****..******...***................
.......*........................***..........
........*..***

Write INF file for : CONTROL.sch


"CONTROL.sch"

**..................*..*...**..*.*..*..*..*..
*..*..*..*..*..*..*..*...*..*..*...*..*..*...
*...*..*..**

WriteInetList: complete

Opening "STATE_4K.sch"
Building Network "STATE_4K.sch"


"STATE_4K.sch"

***............*******
Building Network - 54856 Available Nodes.
*****..******...***....
.............................................
.........*...................................
.***...................*........***

Write INF file for : STATE_4K.sch


"STATE_4K.sch"

**...................*........*...**.........
..................*.....*......*.....*.......
..*....*.....*....*....*.....*....*..*.....*.
...*.....*...*...*...*..*..*..*...*..*..*....
*....*..*..*..*....*..*..**

WriteInetList: complete

Opening "STACK_4K.sch"
Building Network "STACK_4K.sch"


"STACK_4K.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......*.***

Write INF file for : STACK_4K.sch


"STACK_4K.sch"

**............*.*...**...*...*..*..*..*..*..*
..*..*..*..*..*..*..*..**

WriteInetList: complete

XMAKE: Execute command 'sdt2xnf calc.inf calc.xnf -D xnf '.
******************************************************************************
inf2xnf [5.0.0L-03/11/1994]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

+ inf2xnf  @ 1994/03/16 07:55:01 [00:00:07]
  
  + Parameters 
    ----------------------- 
    inffile   = calc.inf 
    xnffile   = calc.xnf 
    p         = 4003PC84-6 
    s         = j:\xc4000\  
    u         = .\  
    d         = xnf\ 
    logfile   = sdt2xnf.log 
    ----------------------- 
  
  Reading the root INF file 'calc.inf' ..... 
  Reading the child-sheet INF file '.\osc_4k.inf' ..... 
  Writing the XNF file 'xnf\osc_4k.xnf' ..... 
  Reading the child-sheet INF file '.\led_inv.inf' ..... 
  Writing the XNF file 'xnf\led_inv.xnf' ..... 
  Reading the child-sheet INF file '.\debounce.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\fd.inf' ..... 
  Writing the XNF file 'xnf\fd.xnf' ..... 
  Writing the XNF file 'xnf\debounce.xnf' ..... 
  Reading the child-sheet INF file '.\7seg_inv.inf' ..... 
  Writing the XNF file 'xnf\7seg_inv.xnf' ..... 
  Reading the child-sheet INF file '.\sw7.inf' ..... 
  Writing the XNF file 'xnf\sw7.xnf' ..... 
  Reading the child-sheet INF file '.\alu.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\adsu4.inf' ..... 
  Writing the XNF file 'xnf\adsu4.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\fd4ce.inf' ..... 
  Writing the XNF file 'xnf\fd4ce.xnf' ..... 
  Reading the child-sheet INF file '.\andblk2.inf' ..... 
  Writing the XNF file 'xnf\andblk2.xnf' ..... 
  Reading the child-sheet INF file '.\orblk2.inf' ..... 
  Writing the XNF file 'xnf\orblk2.xnf' ..... 
  Reading the child-sheet INF file '.\xorblk2.inf' ..... 
  Writing the XNF file 'xnf\xorblk2.xnf' ..... 
  Reading the child-sheet INF file '.\muxblk5.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\m2_1.inf' ..... 
  Writing the XNF file 'xnf\m2_1.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\m4_1e.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\m2_1e.inf' ..... 
  Writing the XNF file 'xnf\m2_1e.xnf' ..... 
  Writing the XNF file 'xnf\m4_1e.xnf' ..... 
  Writing the XNF file 'xnf\muxblk5.xnf' ..... 
  Reading the child-sheet INF file '.\muxblk2.inf' ..... 
  Writing the XNF file 'xnf\muxblk2.xnf' ..... 
  Writing the XNF file 'xnf\alu.xnf' ..... 
  Reading the child-sheet INF file '.\7segdec.inf' ..... 
  Writing the XNF file 'xnf\7segdec.xnf' ..... 
  Reading the child-sheet INF file '.\control.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\cb2cled.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\ftcle.inf' ..... 
  Writing the XNF file 'xnf\ftcle.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\m2_1b1.inf' ..... 
  Writing the XNF file 'xnf\m2_1b1.xnf' ..... 
  Writing the XNF file 'xnf\cb2cled.xnf' ..... 
  Reading the child-sheet INF file '.\state_4k.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\decode8.inf' ..... 
  Writing the XNF file 'xnf\decode8.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\decode4.inf' ..... 
  Writing the XNF file 'xnf\decode4.xnf' ..... 
  Writing the XNF file 'xnf\state_4k.xnf' ..... 
  Writing the XNF file 'xnf\control.xnf' ..... 
  Reading the child-sheet INF file '.\stack_4k.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc4000\ram16x4.inf' ..... 
  Writing the XNF file 'xnf\ram16x4.xnf' ..... 
  Writing the XNF file 'xnf\stack_4k.xnf' ..... 
  Writing the XNF file 'xnf\calc.xnf' ..... 
- inf2xnf  @ 1994/03/16 07:55:14 [00:00:20]
= -------- @ 1994/03/16 00:00:13 [00:00:13]

+ inf2xnf required [692.202] Kbytes of dynamic/allocated memory 
SDT2XNF Version 5.0.0-02/23/1994 -- XILINX CONFIDENTIAL
Copyright (c) 1993 Xilinx Inc. All Right Reserved.

Executing 'inf2xnf calc.inf calc.xnf d=xnf logfile=sdt2xnf.log' .....

Return code from 'inf2xnf calc.inf calc.xnf d=xnf logfile=sdt2xnf.log' = 0

XMAKE: Set the part type to '4003PC84-6' from 'xnf\calc.xnf'.
XMAKE: Running with the following XMAKE options: -V 
  >>>  XDELAY is run always with '-D' and '-W' options by XMAKE.
XMAKE: Makefile saved in 'calc.mak'.

XMAKE: Making 'calc.bit'...
XMAKE: Making 'calc.xff' because it does not exist.

XMAKE: Execute command 'xnfmerge -A -D xnf -D . -P 4003PC84-6 xnf\calc.xnf calc.xff'.
******************************************************************************
XNFMERGE Ver. pre-5.0.0s
(c) Copyright 1987-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.


List of files read
    Read file xnf\calc.xnf
    Read file xnf\stack_4k.xnf
    Read file xnf\ram16x4.xnf
    Read file xnf\control.xnf
    Read file xnf\state_4k.xnf
    Read file xnf\decode4.xnf
    Read file xnf\decode8.xnf
    Read file xnf\m2_1.xnf
    Read file xnf\fd.xnf
    Read file xnf\cb2cled.xnf
    Read file xnf\m2_1b1.xnf
    Read file xnf\ftcle.xnf
    Read file xnf\7segdec.xnf
    Read file xnf\alu.xnf
    Read file xnf\muxblk2.xnf
    Read file xnf\muxblk5.xnf
    Read file xnf\m4_1e.xnf
    Read file xnf\m2_1e.xnf
    Read file xnf\xorblk2.xnf
    Read file xnf\orblk2.xnf
    Read file xnf\andblk2.xnf
    Read file xnf\fd4ce.xnf
    Read file xnf\adsu4.xnf
    Read file xnf\sw7.xnf
    Read file xnf\7seg_inv.xnf
    Read file xnf\debounce.xnf
    Read file xnf\led_inv.xnf
    Read file xnf\osc_4k.xnf
Netlist written to file calc.xff
XMAKE: Making 'calc.xtf' because it does not exist.

XMAKE: Execute command 'xnfprep calc.xff calc.xtf ignore_xnf_locs=IO parttype=4003PC84-6'.
******************************************************************************
xnfprep [pre5.0.0x]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

+ xnfprep  @ 1994/03/16 07:56:10 [00:00:38]
  
  + Parameters 
    ----------------------- 
    design          = calc.xff 
    outfile         = calc.xtf 
    report          = *** 
    savesig         = FALSE 
    parttype        = 4003PC84-6 
    cstfile         = *** 
    logfile         = xnfprep.log 
    ----------------------- 
  
  + Additional Specified or Non-Default Parameters 
    ----------------------- 
    ignore_xnf_locs = io 
    ----------------------- 
  
  xnfprep:  running design rule checker ...
  
  
  xnfprep:  checking XACT-Performance specifications ...
  
  
  xnfprep:  trimming unnecessary and redundant logic...
  
  
  xnfprep:  running design rule checker on trimmed design...
  
  
  xnfprep:  reverifying XACT-Performance specifications in trimmed design ...
  
  
  XNFPREP SUMMARY 
  ---------------
  0 Errors found
  2 Warnings found
  17 Unnecessary inverters and buffers removed
  25 Unnecessary or disabled symbols removed
  14 Sourceless or loadless signals removed
  
  Refer to the calc.prp file for details.
  
  Output netlist written to file calc.xtf.
  
  
- xnfprep  @ 1994/03/16 07:57:07 [00:01:35]
= -------- @ 1994/03/16 00:00:57 [00:00:57]

+ xnfprep required [1224.170] Kbytes of dynamic/allocated memory 

+ Data Manager Auto Save 
  Saving MAP_XNF_TRIM cell "calc" 
- Data Manager Auto Save 
XMAKE: Making 'calc.lca' because it does not exist.

XMAKE: Execute command 'ppr calc.xtf cstfile=calc_4k.cst parttype=4003PC84-6'.
******************************************************************************
ppr [pre-5.0.0p]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

*** Warning [EXPIRE:WARNING]
    This version of the ppr program has a built-in expiration date.  
    It will stop running 56 days from today.



+ ppr  @ 1994/03/16 07:58:02 [00:00:38]
  
  + Parameters 
    ----------------------- 
    design            = calc.xtf 
    outfile           = <design name> 
    parttype          = 4003PC84-6 
    estimate          = FALSE 
    logfile           = ppr.log 
    ----------------------- 
  
  + Additional Specified or Non-Default Parameters 
    ----------------------- 
    seed              = 763804682 
    cstfile           = calc_4k.cst 
    ----------------------- 
    
    Parameter values from the xactinit.dat files
    [Environment Variable XACT = j:\;k:\;o:\;l:\;n:\;m:\]
    --------------------------------------------
    no xactinit.dat parameter values defined
    --------------------------------------------
    
  Reading constraints from file calc_4k.cst 
   
  
  
  ppr:  Reading input design data...
  
  Speedfile version 4000.1, revision 4003.4.
  
  
  ppr:  Mapping function generators...
  

    *** PPR: WARNING 7034: 
          In categories of paths that have NO timing specifications, the design 
          has 34 path end-point pairs.  Note that there may be multiple paths
          between any listed pair of end-points.  To limit the number of paths
          reported in each category, set PPR parameter show_tsi_paths =
          <value>.   
    The end-point pairs are listed in file calc.tsi. To suppress the listing
    of paths for categories with no timing specifications, set PPR parameter
    tsi_show_all=FALSE. 
    Preliminary estimate of device utilization for part  4003PC84: 
    ------------------------------------------------------------------------- 
       33% utilization of I/O pins.                ( 20 of  61) 
       24% utilization of CLB function generators. ( 47 of 200) 
        7% utilization of CLB flip-flops.          ( 14 of 200) 
    ------------------------------------------------------------------------- 
    Device utilization comparison shown for part  4002APC84: 
    ------------------------------------------------------------------------- 
       33% utilization of I/O pins.                ( 20 of  61) 
       37% utilization of CLB function generators. ( 47 of 128) 
       11% utilization of CLB flip-flops.          ( 14 of 128) 
    ------------------------------------------------------------------------- 
    This comparison does not consider packages for which the supporting data 
    files have not been installed. 
    Consult the PPR report file for final device utilization statistics. 
  
  ppr:  Placing logic...
  
    * Improve initial placement: 
    * Optimize the improved placement: 
  
  ppr:  Routing signals...
  
    Begin pre-routing, Phase 2, TIMING=OFF; 20 connections. 
    Begin pre-routing, Phase 3, TIMING=OFF; 2 connections. 
    Begin routing, NO_RIP, TIMING=OFF; 265 connections. 
    Begin fixing 8 unroutes on 1 nets, (8 VCC/GND), TIMING=OFF;  

No more unroutes
    Begin routing 4 pullups, TIMING=OFF 
    
    Design has  0  unroutes.
    

  
  ppr:  Generating .LCA File...
  
  
  ppr:  Making Report File...
  
  Wrote report on the result without delay optimization to calc.rpf. 
  
  ppr:  Routing signals...
  
    Begin pre-routing, Phase 2, TIMING=PATH; 20 connections. 
    Begin pre-routing, Phase 3, TIMING=PATH; 2 connections. 
    Begin routing, NO_RIP, TIMING=PATH; 265 connections. 
    Begin fixing 8 unroutes on 1 nets, (8 VCC/GND), TIMING=PATH; (First LCA
    made) 

No more unroutes
    Improving a   73.6ns  path with 8 pins. 

No more unroutes
    Improving a   73.5ns  path with 10 pins. 
    Begin routing 7 pullups, TIMING=OFF 
    
    Design has  0  unroutes.
    
    ----------------------------------------------------------------------
    Timing analysis summary
    ----------------------------------------------------------------------
    
        Deadline  Actual(*)  Specification
        --------  ---------  ------------- 
          <auto>   73.5ns    DEFAULT_FROM_FFS_TO_FFS=FROM:ffs:TO:ffs 
          <auto>   25.0ns    DEFAULT_FROM_PADS_TO_FFS=FROM:pads:TO:ffs 
          <auto>   38.9ns    DEFAULT_FROM_FFS_TO_PADS=FROM:ffs:TO:pads 
    (*) Note: please run xdelay to confirm the actual path delays computed by
    PPR. 

    *** PPR: WARNING 7028: 
          The design has flip-flops with asynchronous set/reset controls
          (PRE/SD or CLR/RD pins).  When PPR analyzes design timing, it does
          not trace paths through the asynchronous set/reset input and on
          through the Q output.
          
          If you want PPR to control the delay on paths through asynchronous
          set/reset pins, you must split the delay requirement into two
          segments: one ending at the set/reset input, and the other beginning
          at the flip-flop output.
          If you want PPR not to analyze paths that lead to asynchronous
          set/reset pins, attach an IGNORE specification to the pin(s) or
          signal(s).
          
          By default, XDelay reports all paths through asynchronous set/reset
          pins. To prevent XDelay from showing these paths, use FlagBlk
          CLB_Disable_SR_Q on the appropriate flip-flops. 

    *** PPR: WARNING 7029: 
          The design has RAM elements.  When PPR analyzes design timing, it
          does not trace paths through the data or write-enable inputs and on
          through the RAM output.  Such paths are normally of interest only
          when the RAM is being read during a write operation.
          
          If you want PPR to control the delay on paths through the D or WE
          inputs, you must split the delay requirement into two segments: one
          ending at the RAM input pin, and the other beginning at the RAM
          output.
          
          By default, XDelay does not report paths through D or WE pins either. 
          To allow XDelay to show these paths, use FlagBlk CLB_Enable_WE and/or 
          FlagBlk CLB_Enable_DIN on the appropriate RAMs. 

  
  ppr:  Generating .LCA File...
  

    *** PPR: WARNING 10604: 
          A .LCA file already exists.  The old .LCA file will be saved as
          'calc.lcb'. 
  
  ppr:  Making Report File...
  
- ppr  @ 1994/03/16 08:12:54 [00:15:30]
= ---- @ 1994/03/16 00:14:52 [00:14:52]

+ ppr required [4394.379] Kbytes of dynamic/allocated memory 

XMAKE: Execute command 'xdelay -D -W calc.lca'.
******************************************************************************
Xilinx LCA xdelay Ver. 4.8.2
Copyright 1985-1994 Xilinx Inc.  All Rights Reserved.
xdelay: writing calc.lca with delay information...
Loading die/package file...
Loading design file...


Timing nets...

xdelay: No paths traced for design calc.lca...

Xilinx LCA xdelay Ver. 4.8.2 ended normally
XMAKE: Making 'calc.bit' because it does not exist.

XMAKE: Execute command 'makebits calc.lca'.
******************************************************************************
Xilinx LCA MAKEBITS Ver. 4.8.2
Copyright 1985-1994 Xilinx Inc.  All Rights Reserved.
makebits: Making bitstream..
Loading die/package file...
Loading design file...


Timing nets...

Xilinx LCA MAKEBITS Ver. 4.8.2 ended normally

XMAKE: 'calc.bit' has been made.
