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| XILINX APPLICATIONS XAPP021V:  SSC24-4  V2.00              BN-3-31-94 |
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README file for the XC3000A Timer/Counter SSC24-4:
==================================================

Note: A more detailed description of this application can be obtained
from XILINX Applications, phone 800-255-7778 (outside California),
408-879-5199, Fax 408-559-7114. 
  

SSC24-4
-------

This application is a 24-bit presettable Timer/Up-Counter with a resolution 
of 7.4 ns using an XC3000A-6, and 3.7 ns using anXC3100A-3. The counter is 
based a prescaling/state-skipping technique that achieves a very high speed 
and uses LCA resources efficiently. 

It is used for high precision timing applications such as video, radar 
or PLL-based frequency synthesizers. 

Note, that the timer cannot be loaded with values between FFFFFF and 
FFFFE1 (with a few exceptions). The Timer/Counter outputs are non-binary for a 
short time after loading. See the application note for details.


Design files included in directory SSC24-4:

  README          This README file
  SCH\SSC24-4H.1  Top-level Viewlogic V4.1.3a schematic
  SCH\SSC24-4.1   24 Bit Timer/Counter
  SCH\CNT20.1     20 Bit Ripple Counter 
  SCH\CNT20A.1    20 Bit Ripple Counter (see below)
  SCH\DIBIT.1     Dibit for 20-Bit Ripple Counter
  SCH\PRE1.1      First Prescaler for the Timer/Counter
  SCH\PRE2.1      Second Prescaler for the Timer/Counter
  SCH\CORR1.1     First Correction Counter for the Timer/Counter
  SCH\CORR2.1     Second Correction Counter for the Timer/Counter

  SYM\*.1         Viewlogic Symbols
  WIR\*.1         Viewlogic Wire files

  XNF\            Xilinx Netlists.
  SSC24-4H.LCA    Placed and Routed LCA file.
  SSC24-4H.CST    Contraints file for the CLB placement.
  SSC24-4H.XRP    Xdelay timing report using XC3000A-6

Software Versions used:
  DS390 Version 4.1.3a Viewlogic and Interface

Recommended Layout, Routing:

Simple floorplanning will significantly improve the speed of any design.
The automatic place-and-route tool may give adequate results, but to 
achieve the claimed speed, careful relative placement all CLBs has to
be done. For maximum performance, some hand routing may be required, 
although PPR will do a very good job on longline assignment and the use
of zero delay routing resources.  

All CLBs of the prescalers/correction counters should be lined up in a 
column starting at the top row of the LCA device to get easy longline 
access. The-20 bit ripple counter uses one carry CLB and one counter 
CLB for every dibit. The carry chain should use direct connect, and 
therefore, the carry CLBs should be lined up in a column to the left 
of the counter CLBs.
 
The placement constraints file SSC24-4H.CST illustrates a sample block 
placement. 

;Sample Placement Constraints File:
place block SSC24-4/Q0 : AB;
place block SSC24-4/EN : BB;
place block SSC24-4/Q2 : CB;
place block SSC24-4/CORR1/C0 : DB;
place block SSC24-4/CORR1/C1 : EB;
place block SSC24-4/C2 : FB;
place block SSC24-4/CNT20/BIT4_5/CINT : GA;
place block SSC24-4/Q4 : GB;
place block SSC24-4/CNT20/BIT6_7/CINT : HA;
place block SSC24-4/Q6 : HB;
place block SSC24-4/CNT20/BIT8_9/CINT : IA;
place block SSC24-4/Q8 : IB;
place block SSC24-4/CNT20/BIT10_11/CINT : JA;
place block SSC24-4/Q10 : JB;
place block SSC24-4/CNT20/BIT12_13/CINT : KA;
place block SSC24-4/Q12 : KB;
place block SSC24-4/CNT20/BIT14_15/CINT : LA;
place block SSC24-4/Q14 : LB;
place block SSC24-4/CNT20/BIT16_17/CINT : MA;
place block SSC24-4/Q16 : MB;
place block SSC24-4/CNT20/BIT18_19/CINT : NA;
place block SSC24-4/Q18 : NB;
place block SSC24-4/CNT20/BIT20_21/CINT : OA;
place block SSC24-4/Q20 : OB;
place block SSC24-4/CNT20/BIT22_23/CINT : PA;
place block SSC24-4/Q22 : PB;


The recommended routing is now described.
Recommended routing is to first route the TC signal onto a vertical 
longline to the .A inputs of most of the CLBs. The CLKI net must be on
a longline to the .K pins. The net EN should use the third vertical
longline to access the .EC pins. The net SSC24-4/Q3 should use direct
connect.
In the ripple counter, make sure that all COUTxx signals use direct 
connect (.Y pin to .A pin).


Performance:

To analyze the performance, a simulator should be used. If the layout
is implemented as descibed above, the maximum frequency of the Timer/Counter
is limited by the toggle rate of the flip-flops in the first prescaler.

For highest performance,
     - TC must settle in 11 fmax clock periods. 
     - PRE1/CLK to PRE1/EN via net CLKI must settle in 3 fmax clock periods.
     - PRE1/CLK to PRE1/DIV3 via net CLKI must settle in 11 fmax clock
       periods.
     - CORR2/CLKI to PRE1/C2 and PRE1/C1 must settle in 8 fmax clock periods. 
     - Local signals in CORR1 must settle in 16 fmax clock periods.  
     - Local signals in CORR2 must settle in 3 fmax clock periods.  

Additional Notes:

Note 1: For an equally spaced TC pulse, an additional flip-flop clocked by 
	SSC24-4/CNT20/CLKI can be used. See schematic CNT20A.

Note 2: Any warning in WIR2XNF regarding incompatible bus widths can be 
	ignored.

Note 3: All CLB pins have been pre-assigned and locked using CLBMAPs with 
	the PLC attribute in the schematic.


--------------------------------- EOF ----------------------------------------

