library synth;
use synth.stdsynth.all;

entity tri is port (
   signal data_in: in vlbit_vector (7 downto 0);
   signal data_out: out vlbit_vector (7 downto 0);
   signal en, clk: in vlbit);
end tri;

architecture behavior of tri is
   signal datatmp: vlbit_vector (7 downto 0);
   begin
      dff_v (data_in, clk, datatmp);
      data_out <= datatmp when (en = '1') else "ZZZZZZZZ";
   end;


