XMAKE Version pre5.0.0m
Copyright (c) 1989-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

XMAKE: Generating makefile 'calc.mak'...
XMAKE: Profile used is 'n:\data\xdm.pro'.

XMAKE: Execute command 'annotate calc.sch '.
******************************************************************************
Loading configuration file
Annotation
"OrCAD/SDT 386+ v1.10    03-SEP-93"
(C)Copyright 1991,1992,1993 OrCAD, Inc. ALL RIGHTS RESERVED.
Reading Configuration Data File: sdt.bcf
Initial memory allocation: 2000K.
Reading Library: j:\xc3000\XC3000.LIB
Reading Library: j:\xc3000\XC3000O.LIB
Reading Library: j:\xc3000\XBLOX.LIB
Opening "calc.sch"
Opening "OSC_3K.sch"
Opening "LED_TRU.sch"
Opening "DEBOUNCE.sch"
Opening "STACK.sch"
Opening "7SEG_TRU.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATMACH.sch"
Opening "calc.sch"
Opening "calc.sch"
Opening "OSC_3K.sch"
Opening "LED_TRU.sch"
Opening "DEBOUNCE.sch"
Opening "STACK.sch"
Opening "7SEG_TRU.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATMACH.sch"
Annotating "calc.sch"
Annotating "OSC_3K.sch"
Annotating "LED_TRU.sch"
Annotating "DEBOUNCE.sch"
Annotating "STACK.sch"
Annotating "7SEG_TRU.sch"
Annotating "SW7.sch"
Annotating "ALU.sch"
Annotating "ANDBLK2.sch"
Annotating "ORBLK2.sch"
Annotating "XORBLK2.sch"
Annotating "MUXBLK5.sch"
Annotating "MUXBLK2.sch"
Annotating "7SEGDEC.sch"
Annotating "CONTROL.sch"
Annotating "STATMACH.sch"

XMAKE: Execute command 'inet calc.sch '.
******************************************************************************
Incremental NetList
"OrCAD/SDT 386+ v1.10    03-SEP-93"

(C)Copyright 1991,1992,1993 OrCAD, Inc. ALL RIGHTS RESERVED.
Reading Configuration Data File: sdt.bcf
Initial memory allocation: 2000K.
Reading Library: j:\xc3000\XC3000.LIB
Reading Library: j:\xc3000\XC3000O.LIB
Reading Library: j:\xc3000\XBLOX.LIB
Opening "calc.sch"
Opening "OSC_3K.sch"
Opening "LED_TRU.sch"
Opening "DEBOUNCE.sch"
Opening "STACK.sch"
Opening "7SEG_TRU.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATMACH.sch"
Opening "OSC_3K.sch"
Opening "LED_TRU.sch"
Opening "DEBOUNCE.sch"
Opening "STACK.sch"
Opening "7SEG_TRU.sch"
Opening "SW7.sch"
Opening "ALU.sch"
Opening "ANDBLK2.sch"
Opening "ORBLK2.sch"
Opening "XORBLK2.sch"
Opening "MUXBLK5.sch"
Opening "MUXBLK2.sch"
Opening "7SEGDEC.sch"
Opening "CONTROL.sch"
Opening "STATMACH.sch"

Opening "OSC_3K.sch"
Building Network "OSC_3K.sch"


"OSC_3K.sch"

***.......*******
Building Network - 54856 Available Nodes.
**************.****.*.......
.***

Write INF file for : OSC_3K.sch


"OSC_3K.sch"

**.*........*...**............*...*..*....*..
.....*...*..*...*...*....*....**

WriteInetList: complete

Opening "LED_TRU.sch"
Building Network "LED_TRU.sch"


"LED_TRU.sch"

**********
Building Network - 54856 Available Nodes.
**************....****....*....***

Write INF file for : LED_TRU.sch


"LED_TRU.sch"

**....*....*...**........*..*...*..*...*..*..
.*..*...**

WriteInetList: complete

Opening "DEBOUNCE.sch"
Building Network "DEBOUNCE.sch"


"DEBOUNCE.sch"

**********
Building Network - 54856 Available Nodes.
**************...****...*...***

Write INF file for : DEBOUNCE.sch


"DEBOUNCE.sch"

**...*...*...**.....*....*....*..*...*..*..*.
...**

WriteInetList: complete

Opening "STACK.sch"
Building Network "STACK.sch"


"STACK.sch"

***........................*******
Building Network - 54856 Available Nodes.
***********
***..............****............*....***

Write INF file for : STACK.sch


"STACK.sch"

**............*....*...**..............*.....
*.....*.....*.....*..*..*..*..*..*..*..*..*..
*..*..*..*..*..*..*..*...*...*...*...*.....*.
....*..*..*..*..*..*......*......*..*..*..*..
**

WriteInetList: complete

Opening "7SEG_TRU.sch"
Building Network "7SEG_TRU.sch"


"7SEG_TRU.sch"

**********
Building Network - 54856 Available Nodes.
**************.........****........
*.........***

Write INF file for : 7SEG_TRU.sch


"7SEG_TRU.sch"

**........*.........*...**..................*
..*...*..*...*..*...*..*...*...*...*..*...*..
*...*..*...*...**

WriteInetList: complete

Opening "SW7.sch"
Building Network "SW7.sch"


"SW7.sch"

***......*******
Building Network - 54856 Available Nodes.
**************........****...
.....*.......***

Write INF file for : SW7.sch


"SW7.sch"

**........*.......*...**..............*...*..
.*...*...*........*...*...*...*...*...*...*..
.*...*...*...*.......*

WriteInetList: complete

Opening "ALU.sch"
Building Network "ALU.sch"


"ALU.sch"

***...*******
Building Network - 54856 Available Nodes.
*****....******.................
.........***.................................
..........................................*..
.............................................
.............................................
.............................................
.............................................
................***.....................*....
......................***

Write INF file for : ALU.sch


"ALU.sch"

**.....................*.....................
.....*...**.....*.....*......*......*......*.
.....*.......*.......*.......*.......*...*...
*...*...*...*...*...*...*..*...*...*...*...*.
..*...*..*...*...*...*..*...*...*...*...*...*
...*...*...*...*...*...*...*..*..*..*..*..*..
*..*..**

WriteInetList: complete

Opening "ANDBLK2.sch"
Building Network "ANDBLK2.sch"


"ANDBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : ANDBLK2.sch


"ANDBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "ORBLK2.sch"
Building Network "ORBLK2.sch"


"ORBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : ORBLK2.sch


"ORBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "XORBLK2.sch"
Building Network "XORBLK2.sch"


"XORBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************............****.....
.......****

Write INF file for : XORBLK2.sch


"XORBLK2.sch"

**............**...**....*..*..*..*..*..*..*.
.*..*..*..*..*..**

WriteInetList: complete

Opening "MUXBLK5.sch"
Building Network "MUXBLK5.sch"


"MUXBLK5.sch"

**********
Building Network - 54856 Available Nodes.
*****..........******..............
.***.........................................
...........*.................................
.............................................
..........................................***
...........................*....***

Write INF file for : MUXBLK5.sch


"MUXBLK5.sch"

**...........................*....*...**.....
....*.....*..*...*..*..*..*..*.....*..*.....*
.....*..*...*..*..*..*..*..*..*...*..*..*..*.
.*..*..*...*..*..*..*..*..**

WriteInetList: complete

Opening "MUXBLK2.sch"
Building Network "MUXBLK2.sch"


"MUXBLK2.sch"

**********
Building Network - 54856 Available Nodes.
**************.............****....
.........****

Write INF file for : MUXBLK2.sch


"MUXBLK2.sch"

**.............**...**....*..*..*..*.....*..*
..*..*..*..*..*..*..*..**

WriteInetList: complete

Opening "7SEGDEC.sch"
Building Network "7SEGDEC.sch"


"7SEGDEC.sch"

**********
Building Network - 54856 Available Nodes.
**************.....................
.............................................
..............****...........****

Write INF file for : 7SEGDEC.sch


"7SEGDEC.sch"

**...........**...**.........................
.........*.....................*..*..........
..........*..*.................*.............
......*..*..*..*..*..*..*..*..*..*..*..*..*..
*..*..*..*..*..*..*..*..*..*..*..*..*..*..*..
*..*..*..*..**

WriteInetList: complete

Opening "CONTROL.sch"
Building Network "CONTROL.sch"


"CONTROL.sch"

**********
Building Network - 54856 Available Nodes.
*****..******...***................
.......*........................***..........
........*..***

Write INF file for : CONTROL.sch


"CONTROL.sch"

**..................*..*...**..*.*..*..*..*..
*..*..*..*..*..*..*..*...*..*..*...*..*..*...
*...*..*..**

WriteInetList: complete

Opening "STATMACH.sch"
Building Network "STATMACH.sch"


"STATMACH.sch"

**********
Building Network - 54856 Available Nodes.
*****..******...***................
......................................*......
..............................***............
......*.........***

Write INF file for : STATMACH.sch


"STATMACH.sch"

**..................*.........*...**.........
..........*....*......*.....*....*.........*.
...*....*....*....*.....*....*..*...*.....*..
..*...*...*..*..*..*..*..*..*...*..*..*...**

WriteInetList: complete

XMAKE: Execute command 'sdt2xnf calc.inf calc.xnf -D xnf'.
******************************************************************************
inf2xnf [PRE-5.0.0i-02/03/1994]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

+ inf2xnf  @ 1994/03/06 11:44:43 [00:00:06]
  
  + Parameters 
    ----------------------- 
    inffile   = calc.inf 
    xnffile   = calc.xnf 
    p         = 3020PC68-70 
    s         = j:\xc3000\  
    u         = .\  
    d         = xnf\ 
    logfile   = sdt2xnf.log 
    ----------------------- 
  
  Reading the root INF file 'calc.inf' ..... 
  Reading the child-sheet INF file '.\osc_3k.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\cb4ce.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\ftce.inf' ..... 
  Writing the XNF file 'xnf\ftce.xnf' ..... 
  Writing the XNF file 'xnf\cb4ce.xnf' ..... 
  Writing the XNF file 'xnf\osc_3k.xnf' ..... 
  Reading the child-sheet INF file '.\led_tru.inf' ..... 
  Writing the XNF file 'xnf\led_tru.xnf' ..... 
  Reading the child-sheet INF file '.\debounce.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\fd.inf' ..... 
  Writing the XNF file 'xnf\fd.xnf' ..... 
  Writing the XNF file 'xnf\debounce.xnf' ..... 
  Reading the child-sheet INF file '.\stack.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\fd4re.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\fdre.inf' ..... 
  Writing the XNF file 'xnf\fdre.xnf' ..... 
  Writing the XNF file 'xnf\fd4re.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\m4_1e.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\m2_1.inf' ..... 
  Writing the XNF file 'xnf\m2_1.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\m2_1e.inf' ..... 
  Writing the XNF file 'xnf\m2_1e.xnf' ..... 
  Writing the XNF file 'xnf\m4_1e.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\d2_4e.inf' ..... 
  Writing the XNF file 'xnf\d2_4e.xnf' ..... 
  Writing the XNF file 'xnf\stack.xnf' ..... 
  Reading the child-sheet INF file '.\7seg_tru.inf' ..... 
  Writing the XNF file 'xnf\7seg_tru.xnf' ..... 
  Reading the child-sheet INF file '.\sw7.inf' ..... 
  Writing the XNF file 'xnf\sw7.xnf' ..... 
  Reading the child-sheet INF file '.\alu.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\adsu4.inf' ..... 
  Writing the XNF file 'xnf\adsu4.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\fd4ce.inf' ..... 
  Writing the XNF file 'xnf\fd4ce.xnf' ..... 
  Reading the child-sheet INF file '.\andblk2.inf' ..... 
  Writing the XNF file 'xnf\andblk2.xnf' ..... 
  Reading the child-sheet INF file '.\orblk2.inf' ..... 
  Writing the XNF file 'xnf\orblk2.xnf' ..... 
  Reading the child-sheet INF file '.\xorblk2.inf' ..... 
  Writing the XNF file 'xnf\xorblk2.xnf' ..... 
  Reading the child-sheet INF file '.\muxblk5.inf' ..... 
  Writing the XNF file 'xnf\muxblk5.xnf' ..... 
  Reading the child-sheet INF file '.\muxblk2.inf' ..... 
  Writing the XNF file 'xnf\muxblk2.xnf' ..... 
  Writing the XNF file 'xnf\alu.xnf' ..... 
  Reading the child-sheet INF file '.\7segdec.inf' ..... 
  Writing the XNF file 'xnf\7segdec.xnf' ..... 
  Reading the child-sheet INF file '.\control.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\cb2cled.inf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\ftcle.inf' ..... 
  Writing the XNF file 'xnf\ftcle.xnf' ..... 
  Reading the xilinx macro INF file 'j:\xc3000\m2_1b1.inf' ..... 
  Writing the XNF file 'xnf\m2_1b1.xnf' ..... 
  Writing the XNF file 'xnf\cb2cled.xnf' ..... 
  Reading the child-sheet INF file '.\statmach.inf' ..... 
  Writing the XNF file 'xnf\statmach.xnf' ..... 
  Writing the XNF file 'xnf\control.xnf' ..... 
  Writing the XNF file 'xnf\calc.xnf' ..... 
- inf2xnf  @ 1994/03/06 11:44:57 [00:00:20]
= -------- @ 1994/03/06 00:00:14 [00:00:14]

+ inf2xnf required [711.958] Kbytes of dynamic/allocated memory 
SDT2XNF Version PRE-5.0.0i-02/02/1994 -- XILINX CONFIDENTIAL
Copyright (c) 1993 Xilinx Inc. All Right Reserved.

Executing 'inf2xnf calc.inf calc.xnf d=xnf logfile=sdt2xnf.log' .....

Return code from 'inf2xnf calc.inf calc.xnf d=xnf logfile=sdt2xnf.log' = 0

XMAKE: Set the part type to '3020PC68-70' from 'xnf\calc.xnf'.
XMAKE: Running with the following XMAKE options: (none)
XMAKE: Makefile saved in 'calc.mak'.

XMAKE: Making 'calc.bit'...

XMAKE: Execute command 'xnfmerge -A -D xnf -D . -P 3020PC68-70 xnf\calc.xnf calc.xff'.
******************************************************************************
XNFMERGE Ver. pre-5.0.0r
(c) Copyright 1987-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.


List of files read
    Read file xnf\calc.xnf
    Read file xnf\control.xnf
    Read file xnf\statmach.xnf
    Read file xnf\m2_1.xnf
    Read file xnf\fd.xnf
    Read file xnf\cb2cled.xnf
    Read file xnf\m2_1b1.xnf
    Read file xnf\ftcle.xnf
    Read file xnf\7segdec.xnf
    Read file xnf\alu.xnf
    Read file xnf\muxblk2.xnf
    Read file xnf\muxblk5.xnf
    Read file xnf\m4_1e.xnf
    Read file xnf\m2_1e.xnf
    Read file xnf\xorblk2.xnf
    Read file xnf\orblk2.xnf
    Read file xnf\andblk2.xnf
    Read file xnf\fd4ce.xnf
    Read file xnf\adsu4.xnf
    Read file xnf\sw7.xnf
    Read file xnf\7seg_tru.xnf
    Read file xnf\stack.xnf
    Read file xnf\d2_4e.xnf
    Read file xnf\fd4re.xnf
    Read file xnf\fdre.xnf
    Read file xnf\debounce.xnf
    Read file xnf\led_tru.xnf
    Read file xnf\osc_3k.xnf
    Read file xnf\cb4ce.xnf
    Read file xnf\ftce.xnf
Netlist written to file calc.xff

XMAKE: Execute command 'xnfprep calc.xff calc.xtf parttype=3020PC68-70'.
******************************************************************************
xnfprep [pre5.0.0w]  --  Xilinx Automatic CAE Tools
Copyright (c) 1994 Xilinx Inc.  All Rights Reserved. 
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

+ xnfprep  @ 1994/03/06 11:45:54 [00:00:38]
  
  + Parameters 
    ----------------------- 
    design          = calc.xff 
    outfile         = calc.xtf 
    report          = *** 
    savesig         = FALSE 
    parttype        = 3020PC68-70 
    cstfile         = *** 
    logfile         = xnfprep.log 
    ----------------------- 
  
  xnfprep:  running design rule checker ...
  
  
  xnfprep:  trimming unnecessary and redundant logic...
  
  
  xnfprep:  running design rule checker on trimmed design...
  
  
  XNFPREP SUMMARY 
  ---------------
  0 Errors found
  2 Warnings found
  5 Unnecessary inverters and buffers removed
  20 Unnecessary or disabled symbols removed
  17 Sourceless or loadless signals removed
  
  Refer to the calc.prp file for details.
  
  Output netlist written to file calc.xtf.
  
  
- xnfprep  @ 1994/03/06 11:46:42 [00:01:26]
= -------- @ 1994/03/06 00:00:48 [00:00:48]

+ xnfprep required [1356.694] Kbytes of dynamic/allocated memory 

+ Data Manager Auto Save 
  Saving MAP_XNF_TRIM cell "calc" 
- Data Manager Auto Save 

XMAKE: Execute command 'xnfmap -P 3020PC68-70 calc.xtf calc.map'.
******************************************************************************
XNFMAP Ver. pre-5.0.0r
(c) Copyright 1987-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.
Reading file calc.xtf...

Checking network for logical errors...

Preparing design...

Assigning logic to LCA elements...

Preparing GUIDE file...

Checking mapped logic blocks...

DESIGN SUMMARY:
	Part type=3020PC68-70
	52 of 64 CLBs used
	23 of 58 I/O pins used
	0 of 6 internal IOBs used
	0 of 16 internal three-state signals used (0 TBUFS used)

	33  CLB flipflops used

	Total number of WARNINGS generated during mapping = 0.
	Total number of ERRORS generated during mapping = 0.

Writing design file calc.map...

Writing guide file calc.pgf...

XMAKE: Execute command 'map2lca -P 3020PC68-70 calc.map calc.lca'.
******************************************************************************
MAP2LCA Ver. pre-5.0.0r
(c) Copyright 1988-1994 Xilinx Inc. All rights reserved
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.

Checking network for logical errors...
Assigning logic to LCA elements...


SUMMARY: Part type=3020PC68-70
         52 of 64 CLBs used
         23 of 58 I/O pins used
         0 of 6 internal IOBs used
         0 of 16 internal three-state signals used
Design written to file calc.lca (APR constraints in calc.scp)

XMAKE: Execute command 'apr -W -Y calc.lca calc.lca'.
******************************************************************************
AUTOMATIC PLACE AND ROUTE PROGRAM -- Version pre-5.0.0r
Copyright (C) 1986-1994 by Xilinx, Inc.  All Rights Reserved.
386|DOS-Extender 4.1 - Copyright (C) 1986-1993 Phar Lap Software, Inc.
Sun Mar  6 11:47:15 1994
 Input Design File: calc.lca
         Part Type: 3020PC68
       Speed Grade: -70
 Guide Design File: (none)
    Schematic File: calc.scp
  Constraints File: (none)
           Options: -a3 -r4 -s17091 -w -y
Output Design File: calc.lca
       Report File: calc.rpt
      Message File: (none)
Reading input design...
Reading constraints...
Placing blocks...

Initial score: *55265*

Annealing...
Estimated execution time for placement: 00:00:00
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
   34117.8  ****   56283  102%   64573  *****   5.3%    00:00:00
   32675.9   -4%   51160   93%   61435  -4.9%   4.9%    00:00:01
   30051.4   -8%   51160   93%   60498  -1.5%   4.8%    00:00:01
   26460.4  -12%   51160   93%   61390   1.5%   5.7%    00:00:02
   22281.4  -16%   50948   92%   60505  -1.4%   5.1%    00:00:03
   18089.8  -19%   49075   89%   62136   2.7%   7.7%    00:00:03
   13963.7  -23%   49075   89%   62737   1.0%   6.1%    00:00:04
   10255.0  -27%   49075   89%   60281  -3.9%   5.5%    00:00:05
    7338.1  -28%   49075   89%   60978   1.2%   6.2%    00:00:06
    5194.0  -29%   49075   89%   59642  -2.2%   5.3%    00:00:07
    3683.9  -29%   48713   88%   57600  -3.4%   6.1%    00:00:08
    2613.2  -29%   46387   84%   56288  -2.3%   7.1%    00:00:09
    1919.9  -27%   46387   84%   56321   0.1%   5.3%    00:00:11
    1427.5  -26%   46387   84%   53576  -4.9%   5.9%    00:00:12
    1106.2  -23%   43365   78%   52128  -2.7%   6.5%    00:00:13
     896.0  -19%   43365   78%   49999  -4.1%   5.3%    00:00:15
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
     749.7  -16%   42939   78%   47998  -4.0%   3.8%    00:00:16
     630.0  -16%   39768   72%   45883  -4.4%   5.6%    00:00:18
     532.6  -15%   37225   67%   43139  -6.0%   7.2%    00:00:19
     467.2  -12%   37225   67%   42494  -1.5%   5.2%    00:00:21
     417.3  -11%   32306   58%   37026 -12.9%   5.4%    00:00:23
     378.0   -9%   28392   51%   33218 -10.3%   7.1%    00:00:25
     347.5   -8%   28392   51%   33305   0.3%   5.3%    00:00:27
     291.7  -16%   27702   50%   31916  -4.2%   8.4%    00:00:29
     253.3  -13%   27702   50%   32404   1.5%   5.6%    00:00:31
     230.4   -9%   25694   46%   29611  -8.6%   6.3%    00:00:33
     209.7   -9%   25694   46%   28482  -3.8%   3.7%    00:00:35
     182.7  -13%   23895   43%   26783  -6.0%   6.8%    00:00:37
     161.9  -11%   23385   42%   25141  -6.1%   2.9%    00:00:39
     147.8   -9%   23385   42%   26114   3.9%   2.2%    00:00:42
     145.6   -1%   21982   40%   23492 -10.0%   3.5%    00:00:44
     145.5   -0%   21716   39%   23502   0.0%   2.8%    00:00:47
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
     149.9    3%   21220   38%   23643   0.6%   3.5%    00:00:49
     135.8   -9%   21220   38%   23605  -0.2%   3.0%    00:00:52
     124.8   -8%   21143   38%   22608  -4.2%   3.0%    00:00:55
     120.0   -4%   20735   38%   21959  -2.9%   2.4%    00:00:58
     104.7  -13%   19833   36%   21418  -2.5%   2.8%    00:01:00
      93.4  -11%   19553   35%   20969  -2.1%   3.0%    00:01:03
      84.6   -9%   19553   35%   20747  -1.1%   2.0%    00:01:06
      76.3  -10%   19530   35%   20450  -1.4%   2.0%    00:01:09
      65.7  -14%   19472   35%   20467   0.1%   2.4%    00:01:12
      59.3  -10%   18842   34%   19434  -5.0%   1.5%    00:01:15
      54.5   -8%   18635   34%   19185  -1.3%   1.8%    00:01:19
      50.8   -7%   18635   34%   19126  -0.3%   0.8%    00:01:22
      47.8   -6%   18092   33%   18794  -1.7%   2.0%    00:01:25
      45.6   -5%   17980   33%   18413  -2.0%   0.9%    00:01:29
      42.4   -7%   17980   33%   18494   0.4%   1.2%    00:01:32
      39.3   -7%   17827   32%   18187  -1.7%   1.1%    00:01:36
--------------------------------------------------------------------
                    Best  % of    Avg                   Placement
      Temp  %Chng  Score  Init   Score  %Chng  Stdev    CPU time
--------------------------------------------------------------------
      37.3   -5%   17750   32%   18032  -0.9%   0.9%    00:01:39
      35.3   -5%   17524   32%   17876  -0.9%   0.9%    00:01:43
Quenching...
       0.0  ****   17508   32%   17509  -2.1%   0.0%    00:01:46
       0.0  ****   17508   32%   17508  -0.0%   0.0%    00:01:50
       0.0  ****   17508   32%   17508   0.0%   0.0%    00:01:53

Final score: *17508*

Total Placement CPU time: 00:01:53

Adopting new placement...
Writing placed but unrouted design...
Assigning long lines...
Routing nets...

	Iteration 1...
	Using delay-driven detail router...
	Detail Routing (with Rip-up & Retry Routing)...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	Rip-up & Retry Routing and Routing Improvement
	on 0 unrouted load pins in unwritten design...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.
	Routing CPU time: 00:00:17
	Writing new design...

	Placement Improvement...
	Using delay-driven detail router...
	Percent blks scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.
	Routing CPU time: 00:00:23
	Writing new design...

	Timing Improvement...
	Using delay-driven detail router...
	Exhaustive Rip-up Retry...
	Percent nets scanned: 10%..20%..30%..40%..50%..60%..70%..80%..90%..100%
	There are 0 unrouted load pins.

Total Routing CPU time: 00:01:18

Checking results...
Timing nets...
Writing report...
Writing new design...

Total elapsed time: 0 hrs, 3 mins, 24 secs

There are 0 unrouted load pins.
Done.
Sun Mar  6 11:50:38 1994

XMAKE: Execute command 'makebits -S0 -R2 -XB -YA calc.lca'.
******************************************************************************
Xilinx LCA MAKEBITS Ver. 4.8.0
Copyright 1985-1994 Xilinx Inc.  All Rights Reserved.
makebits: Making bitstream..
Loading die/package file...
Loading design file...


Timing nets...

Xilinx LCA MAKEBITS Ver. 4.8.0 ended normally

XMAKE: 'calc.bit' has been made.
