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| XILINX APPLICATIONS XAPP003V:  CFSD8-V2.00                BN-3-18-94  |
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README file for the XC3000A Counter CFSD8:
==========================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.


CFSD8
------

  This counter is an-8 bit Loadable Down Counter/Rate Divider.  It is called a
rate divider because it reloads the state on the D inputs when the terminal 
count of all zeros is reached.  The counter has a PRESET input to force the 
counter to load the current state on the D inputs. All signals are active-High 
except for the TCB (terminal count).  

  The operation of the counter is based on 2-bit count cells in a single CLB.  
Each of the cells receives two T inputs, Tn and Tn+1, that tell the Qn and 
Qn+1 bits whether to toggle.  Each cell also has two D inputs, Dn and Dn+1, to 
be used when the counter is being reloaded or preset via the TCB input.  

  Parallel decoding is done on the Q0 through Q7 bits in additional CLBs to 
produce the toggle lines T2 through T7 and TCB. The TCB signal is pipelined 
by one register and hence decodes the state of 01 hex.  This allows the TCB 
line to be routed without the burden of an additional CLB delay.  Also, 
because of this the counter can not be reloaded or preset to 00 hex.  For a D0 
through D7 value of Nn the TCB line will go low for one clock cycle every N+1 
clock cycles.

  This counter will run at 42 MHz in the XC3000A-6, and at 63 MHz in the 
XC3100A-3.

Design files included in directory CFSD8:

  README         This README file
  SCH\CFSD8H.1   Top-level Viewlogic V4.1.3a schematic
  SCH\CFSD8.1    8 Bit Presettable Up Counter              (Sheet 1)
  SCH\CFSD8.2    CLBMAPs for the counter                   (Sheet 2)
  SYM\*.1        Viewlogic Symbol for Counter
  WIR\*.1        Viewlogic Wire files

  XNF\           Xilinx Netlists for High Level Schematic
  CFSD8H.LCA     Placed and Routed LCA file
  CFSD8H.CST     Contraints file for the CLB placement.
  CFSD8H.XRP     Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Recommended Layout, Routing:

   Simple floorplanning will significantly improve the performance of any 
design. For this counter, the CFSTA/T04Q01-04 CLB should be placed close 
to the Q00_01, Q02_03, and Q04_05 CLBs with these CLBs in a tight cluster 
to minimize the Q0 through Q4 nets to CLB CFSTA/T04Q01-04.

The T06_07, and TCB CLBs should be placed close to CLB CFSTA/T04Q01-04
since this CLB drives them both.  Just to the right of the first cluster
should be the CFSTA/(T02_03 and T05).  Then the Q06_07 CLB is placed below
the CFSTA/T06_07 CLB.
 
 The placement is listed below:

place block Q0 : CC;
place block Q2 : DC;
place block Q4 : CD;
place block Q6 : DE;
place block CFSTA/T2 : CB;
place block CFSTA/T4 : DD;
place block CFSTA/T5 : BD;
place block CFSTA/T6 : CE;
place block TCB : EE;

   For maximum performance, some hand routing may be required, although 
PPR will do a very good job on longline assignment and the use of zero delay
routing resources.
 
   The recommended routing is now described.  The longest logic path is
from the Q0 - Q4 bits through the CFSTA/T04Q01_04 CLB through the
CFSTA/T06_07 CLB to the count bits of CLB Q06_07.  Therefore, one should
route the Q0 - Q4 signals to the CFSTA/T04Q01_04 CLB.  These nets must be
kept as short as possible.  Then route the CFSTA/Q1-4 signal to CFSTA/T06_07
again with a short delay.  Next, route the CFSTA/(T6 and T7) signals.  The
other CFSTA/TXX nets may be routed next followed by the Q5 through Q7
signals.  It is recommended that the RoutePin (rp) command in XACT be used
to route the Q0 through Q4, CFSTA/Q1-4, and CFSTA/(T6 and T7) signals.  Also
care should be taken that additional loads on Q0 through Q4 do not degrade
these net delays going to CLB CFSTA/T04Q01_04.  


Performance:

XDELAY was used to report all clock-to-set-up paths. See the .XRP file.

