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| XILINX APPLICATIONS XAPP002V: CLDF16-V2.00                     BN-3-17-94  |
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README file for the XC3000A Counter CLDF16:
===========================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.


CLDF16
------

This counter is a 16-bit Loadable Up/Down Counter with a Clock Enable (CE),
Parallel Load (PE), Up/Down Control (UP), Clock (CLK) and an asynchronous
reset (RST).  The difference between this and the CLDBxx counters is that the 
carry from the lower 8 bits of the counter is used as a parallel enable for 
the upper 8 bits of the counter.  All signals are active-High.  The operation 
of the counter is based on passing a carry for each group of 2 bits to higher 
group of 2 bits. This carry is based on a carry in (CEOxx) from the previous 
2 bit, the count direction and the current state of the 2 bits. 

The counter in general is broken into 2-bit sections with 2 CLBs each. The 
first CLB in a section contains 2 bits of the counter with its enable logic.  
The second CLB contains a carry to the next set of 2 CLBs and a carry to 
the MSB of the current pair of counter bits. 

The upper 8 bits of the counter also use the parallel enable .EC inputs
derived from the OR of the carry out of the lower 8 bits and the PE line.
The ORing in of the PE allows the counter to be re-loaded on any clock cycle
since otherwise the upper 8 bits of the counter would not necessarily be
enabled when re-loading is desired.  This technique increases the performance.

The speed of the counter is determined by the carry path from the CE, UP,
Q1, and Q0 signals to the carry input of the Q6 and Q7 logic block.
The speed is also determined by the carry path from the CE, UP, Q8, and Q9 
signals to the carry input of the Q14 and Q15 logic block.  

With careful layout of the CLBs to minimize the carry delays the performance
of the counter exceeds 28 MHz in the XC3000A-6 and 41 MHz in the XC3100A-3. 

Because a high level schematic was used, the CLB and net names carry the 
prefix CLDBA/.


Design files included in directory CLDF16:

  README         This README file.
  SCH\CLDF16H.1  Top-level Viewlogic V4.1.3a schematic (Sheet 1)
  SCH\CLDF16.1   16 Bit Loadable Up/Down Counter    (Sheet 2)
  SCH\CLDF16.2   CLBMAPs for Counter
  SYM\*.1        Viewlogic Symbol for Counter
  WIR\*.1        Viewlogic Wire files

  XNF\           Xilinx Netlist for High Level Schematic
  CLDF16H.LCA    Placed and Routed LCA file
  CLDF16H.CST    Contraints file for the CLB placement.
  CLDF16H.XRP    Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface


Recommended Layout, Routing:

The recommended CLB placement for highest performance is listed below and in 
the constraints file CLDF16H.CST.  The placement generally goes from LSB
to MSB down the first column for the counter CLBs, Qxx, and down the second
column for the carry CLBs, CLDBA/CEOxx.  This is for the lower 8 bits of
the counter.  One should take note of the placement CLDBA/CEO6 and CLDBA/CEO7
CLBs. The carries are routed out of the .Y output of the CLDBA/CEOxx
into the .A inputs of the next CLDBA/CEOxx CLB in the carry chain.  They
also go into the next count CLB, Qxx.  The upper 8 bits of the counter follow
similarly. For maximum performance, the long lines need to be routed by hand.


;Placement Constraints File:
place block CLDBA/CEO1 : AB;
place block CLDBA/CEO3 : BB;
place block CLDBA/CEO5 : CB;
place block CLDBA/CEO6 : DB;
place block CLDBA/CEO7 : DC;
place block CLDBA/CEO9 : EB;
place block CLDBA/CEO11 : FB;
place block CLDBA/CEO13 : GB;
place block CLDBA/CEO15 : HB;

place block Q0 : AA;
place block Q2 : BA;
place block Q4 : CA;
place block Q6 : DA;
place block Q8 : EA;
place block Q10 : FA;
place block Q12 : GA;
place block Q14 : HA;


Implications of logic on routing:

The longest path is from the LSB Q outputs through the carry chain to the
CLB containing the Q6 and Q7 input logic and the path to be minimized.  The
CE and UP signals from the pads must also enter this logic path so their nets
going into the LSB carry logic should be minimized.  The same applies 
to the upper 8 bits of the counter with regard the CE and UP signals.
These paths should be short to the CLDBA/CEO9 CLB.  The upper 8 bits are
parallel count enabled with the CLDBA/CEO6 signal (which contains PE in its
logic).  The CLDBA/CEO6 signal is on a long line and goes to the .EC inputs
of the upper bits of the counter.

Recommended routing:

The UP and CE signals should be routed with minimum delay to the CLDBA/CEO1,
and CLDBA/CEO9 CLBs.  The CLDBA/CEO6 (Upper bits parallel enable) should be
routed with minimum delay to the .EC inputs.  Also minor care should be
observed to not make the PE input swamp out the gains made above.  The same
is true of the UP signal to the other CLBs.  The UP signal can be put on a
long line so that some of the lower bit carry paths in the counter again don't 
swamp out the gains made by routing quickly to the CLBs mentioned above.  The 
CEOxx bits in the long carry chain have been flagged critical in the schematic 
and the blocks were placed to allow direct connects for these carries.  


Performance:

   The performance was analyzed using XDELAY to report all clock-to-set-up
paths.
