 
XEPLD, Version 5.0                                          Xilinx Inc.
                                 Mapping Report
 Circuit name: UART
Target Device: XC7354-10PC68                  Integrated:  1-13-94, 12:49PM

                                                                          
Function Block 1              Fast inputs  -  0/12    Shared pterms -  0/0 
                              Total inputs -  0/24    Macrocells    -  0/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
.                                              FB1-1         4         .  
.                                              FB1-2         12        .  
.                                              FB1-3         13        .  
.                                              FB1-4         15        .  
.                                              FB1-5         17        .  
.                                              FB1-6         19        .  
.                                              FB1-7         21        .  
.                                              FB1-8         22        .  
.                                              FB1-9         23        .  
                                                                          
Function Block 2              Fast inputs  -  0/12    Shared pterms -  0/0 
                              Total inputs -  4/24    Macrocells    -  1/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
$1I203                              :PIN18_INV FB2-1         66        .  
.                                              FB2-2         58        .  
.                                              FB2-3         57        .  
.                                              FB2-4         56        .  
.                                              FB2-5         55        .  
.                                              FB2-6         52        .  
.                                              FB2-7         51        .  
.                                              FB2-8         48        .  
.                                              FB2-9         46        .  
                                                                          
Function Block 3              Fast inputs  -  0/3     Shared pterms -  1/12
                              UIM inputs   - 16/21    Macrocells    -  9/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
DESERIALIZER                        :QC        FB3-1         .         .  
                                    :QD        FB3-2         .         .  
DOUT7                                          FB3-3         60        O  
DOUT6                                          FB3-4         61        O  
DOE                                            FB3-5         62       I/O 
DOUT5                                          FB3-6         64        O  
DESERIALIZER                        :QE        FB3-7         44        .  
FREQ_DIVIDER[CB8RE]                 :Q4        FB3-8         45        .  
                                    :Q5        FB3-9         47        .  
                                                                          
Function Block 4              Fast inputs  -  0/3     Shared pterms -  1/12
                              UIM inputs   - 15/21    Macrocells    -  9/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
START                                          FB4-1         38        O  
READY                                          FB4-2         53        O  
PARITY                                         FB4-3         54        O  
FREQ_DIVIDER[CB8RE]                 :Q1        FB4-4         .         .  
                                    :Q2        FB4-5         .         .  
                                    :Q3        FB4-6         .         .  
OVERUN                                         FB4-7         39        O  
FRAMING                                        FB4-8         40        O  
BYTECLK                                        FB4-9         42        O  
                                                                          
Function Block 5              Fast inputs  -  0/3     Shared pterms -  1/12
                              UIM inputs   -  4/21    Macrocells    -  3/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
DESERIALIZER                        :QA        FB5-1         32        .  
                                    :QB        FB5-2         33        .  
FREQ_DIVIDER[CB8RE]                 :Q0        FB5-3         35        .  
.                                              FB5-4         37        .  
.                                              FB5-5         16        .  
.                                              FB5-6         18        .  
.                                              FB5-7         25        .  
.                                              FB5-8         31        .  
.                                              FB5-9         36        .  
                                                                          
Function Block 6              Fast inputs  -  0/3     Shared pterms -  0/12
                              UIM inputs   - 12/21    Macrocells    -  9/9 
                                                                          
Function                                       Macrocell     Pkg      Pin 
Name                                           Location      Pin      Use 
--------                                       ---------     ---      --- 
BITCLK                                         FB6-1         27        O  
DESERIALIZER                        :QF        FB6-2         28        .  
                                    :QG        FB6-3         8         I  
DOUT4                                          FB6-4         9         O  
DOUT3                                          FB6-5         10        O  
DESERIALIZER                        :QH        FB6-6         29        .  
DOUT2                                          FB6-7         6         O  
DOUT1                                          FB6-8         24        O  
DOUT0                                          FB6-9         26        O  
                                                                          

Power estimation parameters: MCLP =  14, MCHP =  31.
MCLP represents macrocells in low power mode and
MCHP represents macrocells in high power mode.
Macrocells in unused function blocks are not considered.
MCLP and MCHP are used to estimate chip power consumption.
Consult the proper data sheets for this calculation.

 End of Mapping Report

