GENERAL INFORMATION:

Design:              UARTTOP
Compatible software: Workview v4.1 or Powerview v5.0
                     XEPLD fitter from XACT v5.0
                     Xilinx Viewlogic Interface v5.0

Platform:            PC or Sun
Target device:       XC7354-68 or larger (any speed)

The UARTTOP tutorial demonstrates a purely schematic-based EPLD design flow.
The logic of a UART receiver is expressed by a hierarchical Viewlogic schematic. 
The UARTTOP schematic contains a custom symbol representing the control logic 
defined in the RCVRSUB schematic. (The UARTTOP design contains the same logic 
as the PAL-based UART design.)

FUNCTIONAL SIMULATION FLOW:

The UARTTOP tutorial directory contains ViewSim command files for 
running functional simulation on the UARTTOP design before it is implemented. 
A functional simulation netlist is generated from the UARTTOP and RCVRSUB 
schematics using the Viewlogic VSM command as follows:

  1. In Viewlogic, open the uarttop schematic.
  2. Invoke VSM for uarttop. (In Workview, select Export -> Wirelist -> Viewsim.)
     A ViewSim netlist, uarttop.vsm, is generated.
  3. Invoke the ViewSim simulator and read the uarttop.vsm netlist.
  4. In ViewSim, type "uarttop" to execute the uarttop.cmd file.
  5. Type "Run".
  6. View the result by opening a ViewWave (or ViewTrace) window to display 
     the uarttop.wfm file generated by ViewSim.

DESIGN IMPLEMENTATION FLOW:

The UARTTOP schematic is converted into an xnf netlist and read into the 
XEPLD software using the XEMAKE command as follows:

  1. In XDM, select Translate -> XEMAKE.
  2. Select Done when options are listed.
  3. Select "uarttop.1" from the list of design names.
  4. Select "Make design database" as the target.

XEMAKE automatically invokes the Viewlogic interface, which generates the xnf 
netlist file. It then invokes the EPLD fitter (FITNET) to implement the 
design. The fitter generates a design database file (uarttop.vmh) representing 
the implemented design. The fitter produces several report files, including 
Resources (.res), Mapping (.map), Pinlist (.pin), and Partitioning (.par), all 
provided in this directory as examples (uarttop.*). You can now proceed with 
timing simulation of the implemented design using the same procedure as 
described for the UART tutorial design.

DOCUMENTATION REFERENCE:

A complete description of the UARTTOP design tutorial is provided in Session 6 
of the XEPLD Tutorial chapter of the Xilinx Viewlogic Interface User Guide.

