module datareg 
title '8-Bit 3-state Output Data Register for UART Receiver Design
       Xilinx EPLD Applications, Feb. 93'

        datareg  device  'p20V8r';

" Inputs
  byteclk                   pin 1;      " Parallel data strobe (from rcvr)
  d0,d1,d2,d3,d4,d5,d6,d7   pin 2,3,4,5,6,7,8,9; " Parallel data from shifter
  read                      pin 13;     " Read enable (from cntr6, active-high)

" Outputs
  dout0,dout1,dout2,dout3,dout4,dout5,dout6,dout7 
    pin 22,21,20,19,18,17,16,15 istype 'reg';
      " 3-state register outputs (external)
                                     
" Variables
  data = [dout0..dout7];

Equations

data := [d0..d7];       " Load register on rising edge of byteclk
data.clk = byteclk;
data.oe = read;        " Active-low output enable

end 
