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| XILINX APPLICATIONS XAPP002V:  CLDB16-V2.00               BN-3-16-94  |
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README file for the XC3000A Counter CLDB16:
===========================================

Note: A more detailed description of this application can be found in
Section 8 of the Xilinx Data Book.


CLDB16
------

This counter is a 16-bit Up/Down Loadable Counter with a Clock Enable (CE),
Parallel Load (PE), Up/Down Control (UP), Clock (CLK) and an asynchronous
reset (RST).  All signals are active-High.  The operation of the counter is
based on passing a carry for each group of 2 bits to higher order bits.This 
carry is based on a carry in (CEOxx),  the count direction and the current 
state of the 2 bits.  The speed of the counter is determined by the carry path 
from the CE, UP, Q1, and Q0 signals to the carry input of the most significant 
bits of the counter.  

The counter is broken into 2-bit sections with 2 CLBs each.  The first CLB in
a section contains 2 bits of the counter with its enable logic.  The second 
CLB contains a carry to the next set of 2 CLBs and a carry to the MSB of the 
current pair of counter bits.  The application note shows this for one of the 
groups of 2 bits.  With careful layout of the CLBs to minimize the carry 
delays the speed of the counter exceeds 20 MHz in the XC3000A-6 and 29 MHz in 
the XC3100A.6.  Because a high-level schematic was used, the CLB and net names 
carry the prefix CLDBA/.

Design files included in directory CLDB16:

  README         This README file.
  SCH\CLDB16H.1  Top-level Viewlogic V4.1.3a schematic
  SCH\CLDB16.1   16-Bit Loadable Up/Down Counter
  SCH\CLDB16.2   CLBMAPs for Counter
  SYM\*.1        Viewlogic Symbol for Counter
  WIR\*.1        Viewlogic Wire files

  XNF\           Xilinx Netlist for High Level Schematic
  CLDB16H.LCA    Placed and Routed LCA file
  CLDB16H.CST    Contraints file for the CLB placement.
  CLDB16H.XRP    Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Recommended Layout, Routing:

The recommended layout is listed in the constraints file CLDB16H.CST.  The 
placement generally goes from LSB to MSB down the first column for the counter 
CLBs, Qxx, and down the second column for the carry CLBs, CLDBA/CEOxx.  The 
carries are routed out of the .Y output of the CLDBA/CEOxx into the .A inputs 
of the next CLDBA/CEOxx CLB in the carry chain.  They also go into the next 
count CLB, Qxx.  The longest path from the LSB Q outputs through the carry 
chain to the MSB Q input logic is the path to be minimized.  The CE and UP 
signals from the pads must also enter this long logic path so their nets going 
into the LSB carry logic is minimized. For maximum performance, the long lines 
need to be routed by hand.  

;Placement Constraints File:
place block CLDBA/CEO1 : AB;
place block CLDBA/CEO3 : BB;
place block CLDBA/CEO5 : CB;
place block CLDBA/CEO7 : DB;
place block CLDBA/CEO9 : EB;
place block CLDBA/CEO11 : FB;
place block CLDBA/CEO13 : GB;
place block CLDBA/CEO15 : HB;

place block Q0 : AA;
place block Q2 : BA;
place block Q4 : CA;
place block Q6 : DA;
place block Q8 : EA;
place block Q10 : FA;
place block Q12 : GA;
place block Q14 : HA;

   Recommended routing is to route CE and UP as directly as possible to the
Q0 CLB and the CLDBA/CEO0 CLB (UP only going to the latter CLB).  The UP
signal should be routed to the other CLBs on a long line so that some
of the lower bit carry paths in the counter still don't swamp out the gains
made by routing quickly to the CLBs mentioned above. The CEOxx bits in the
long carry chain have been flagged critical in the schematic and the blocks
were placed to allow direct connects for these carries.

Performance:

   The performance was analyzed using XDELAY to report all clock-to-set-up
paths.
