;--------------------------------------------------------------------
; C3XMMRS.ASM
; Keith Larson
; TMS320 DSP Applications
; (C) Copyright 1995,1996
; Texas Instruments Incorporated
;
; This is unsupported freeware with no implied warranties or
; liabilities.  See the disclaimer document for details
;
; MMR address locations for the TMS320C30 and TMS320C31
;
; Use a .include "C3XMMRS.ASM" within your application code
; to define the locations of the following locations
;--------------------------------------------------------------------
DMA_ctrl  .set 0x808000;  DMA cntl
DMA_srce  .set 0x808004;  DMA srce address
DMA_dest  .set 0x808006;  DMA dest address
DMA_xfr   .set 0x808008;  DMA xfer counter
T0_ctrl   .set 0x808020;  TIM0 gl control
T0_count  .set 0x808024;  TIM0 count
T0_prd    .set 0x808028;  TIM0 prd
T1_ctrl   .set 0x808030;  TIM1 gl control
T1_count  .set 0x808034;  TIM1 count
T1_prd    .set 0x808038;  TIM1 prd
S0_gctrl  .set 0x808040;  SP 0 global control
S0_xctrl  .set 0x808042;  SP 0 FSX/DX/CLKX port ctl
S0_rctrl  .set 0x808043;  SP 0 FSR/DR/CLKR port ctl
S0_tctrl  .set 0x808044;  SP 0 R/X timer control
S0_tcount .set 0x808045;  SP 0 R/X timer counter
S0_tprd   .set 0x808046;  SP 0 R/X timer period
S0_xdata  .set 0x808048;  SP 0 Data transmit
S0_rdata  .set 0x80804C;  SP 0 Data receive
S1_gctrl  .set 0x808050;  SP 1 global control
S1_xctrl  .set 0x808052;  SP 1 FSX/DX/CLKX port ctl
S1_rctrl  .set 0x808053;  SP 1 FSR/DR/CLKR port ctl
S1_tctrl  .set 0x808054;  SP 1 R/X timer control
S1_tcount .set 0x808055;  SP 1 R/X timer counter
S1_tprd   .set 0x808056;  SP 1 R/X timer period
S1_xdata  .set 0x808058;  SP 1 Data transmit
S1_rdata  .set 0x80805C;  SP 1 Data receive
e_buscon  .set 0x808060;  Exp bus control
p_buscon  .set 0x808064;  Pri bus control
;
; Kernel functions can be accessed through the function
; jump table which holds the address of each function
;
JJUMP    .set    0x809ff4    ;<- Base address
JXWRIT   .set    0x809ff5    ;
JXREAD   .set    0x809ff6    ;
JXCTXT   .set    0x809ff7    ;
JXRUNF   .set    0x809ff8    ;
JXSTEP   .set    0x809ff9    ;
JXHALT   .set    0x809ffA    ;
JW_HOST  .set    0x809ffB    ;
JR_HOST  .set    0x809ffC    ;
JSPARE   .set    0x809ffd    ;
