DBG_NUL		equ	$768000	;JTAG cmd, DEBUG for 1 device
				;  most significant 4 bits are actual
				;  JTAG command. 1 bit is don't care
				;  next 4 bits are dummy debug response
ONC_NUL		equ	$668000	;JTAG cmd, OnCE for 1 device
				;  most significant 4 bits are actual
				;  JTAG command. 1 bit is don't care
				;  next 4 bits are dummy debug response
DBG_OK		equ	$dd0000	;JTAG reponse if devices are in debug
DBG_BYP		equ	$7f0000	;JTAG cmd, places odd devices (1,3,etc)
				;  in DEBUG, even devices (2,4,etc) in BYPASS
ONC_BYP		equ	$6f0000	;JTAG cmd, places odd devices (1,3,etc)
				;  in OnCE, even devices (2,4,etc) in BYPASS
BYP_DBG		equ	$f70000	;JTAG cmd, places odd devices (1,3,etc)
				;  in BYPASS, even devices (2,4,etc) in DEBUG
BYP_ONC		equ	$f60000	;JTAG cmd, places odd devices (1,3,etc)
				;  in BYPASS, even devices (2,4,etc) in OnCE

BYP_BYP		equ	$ff0000	;JTAG cmd, places adjacent devices in BYPASS
ONC_ONC		equ	$660000	;JTAG cmd, places adjacent devices in OnCE
DBG_DBG		equ	$770000	;JTAG cmd, places adjacent devices in DEBUG

DEBUG_REQ	equ	$700000	;
ENABLE_ONCE	equ	$600000	;
J_BYPASS        equ	$f00000	;

txwait	MACRO
	jclr	#TDE,SSISR,*	;wait until done sending
	jclr	#RDF,SSISR,*	;wait until done receiving
	ENDM

xmit	MACRO	dreg		;data to xmit must be in upper 8 bits of dreg
	move	dreg,TX		;transmit data
	txwait			;wait until done
	move	RX,dreg		;read data received
	ENDM

recv	MACRO	dreg		;will receive data into dreg
	xmit	dreg		;sending and receiving are the same
	ENDM
