"$IOPd: cc.abl,v 1.3 1992/11/25 15:19:05 dave Exp $
      module ucc 

title ' On-Chip Emulator Command Converter
       MOTOROLA DSP DIVISION 08-9-1996'
"       Rev. 9.1

" Description
"       These equations are used on the command converter for
"       decoding the address of the device, generating interrupts,
"       and controlling the treset signal on the jtag connector.
"       Small changes have been made to accommodate the new multiple
"       target CC interface.  The new CC is now a 56002 and the
"       IRQA from the host is now an NMI.

" Declarations
                ucc          device      'P20V8';

" Inputs
" NOTE: pb12 is used to select between once and jtag protocol
"       pc5 is used for jtag treset
"       pc5 is used to toggle the DEZ and DR lines
"       pc7 (tdo_dso) is dsck input for once, used to generate irqb
"       dez is bidrectional, input used to generate irqb, output used to generate debug req.

                pc5             pin     1;
                p0              pin     2;
                p1              pin     3;
                p2              pin     4;
                admbrk          pin     5;
                pb12            pin     6;
                sel0            pin     7;
                sel1            pin     8;
                sel2            pin     9;
                adm_all         pin     10;
                pc7             pin     11;
                hostenable      pin     13;
                admreset        pin     14;
                pb9             pin     18;
                hostack         pin     23;

" Outputs
                moda_irqa       pin     15;
                resetout        pin     16;
                cc_sel_1        pin     19;
                modb_irqb       pin     20;
                sel_2           pin     21;
                trst            pin     22;
                dez             pin     17;


        H,L,X,C,Z = 1,0,.X.,.C.,.Z.;                "define states

                s0 = !p2 & !p1 & !p0 & !sel2 & !sel1 & !sel0 & !hostenable;
                s1 = !p2 & !p1 &  p0 & !sel2 & !sel1 &  sel0 & !hostenable;
                s2 = !p2 &  p1 & !p0 & !sel2 &  sel1 & !sel0 & !hostenable;
                s3 = !p2 &  p1 &  p0 & !sel2 &  sel1 &  sel0 & !hostenable;
                s4 =  p2 & !p1 & !p0 &  sel2 & !sel1 & !sel0 & !hostenable;
                s5 =  p2 & !p1 &  p0 &  sel2 & !sel1 &  sel0 & !hostenable;
                s6 =  p2 &  p1 & !p0 &  sel2 &  sel1 & !sel0 & !hostenable;
                s7 =  p2 &  p1 &  p0 &  sel2 &  sel1 &  sel0 & !hostenable;

                jtagreset  =  !pc5 & pb12;
                onceacq    = !pb12 & !pc7;
                jtagacq    =   pc5 &  pb12 & !dez;
                dez_assert =  !pc5 & !pb12;


equations

"moda/irqa is the signal that generates a host computer service request
        !moda_irqa = !cc_sel_1 & admbrk & resetout;

"resetout is the signal that drives a reset signal low to the command converter
        !resetout  = !cc_sel_1 & admreset;

"trst is the signal that generates the jtag reset signal to the target.
        !trst     = jtagreset & !cc_sel_1 & resetout;

"dez is bidirectional and is used to send debug requests and receive debug acks.
        dez.oe     = !pc5 & resetout;
        !dez       = dez_assert;

"modb_irqb is the signal that generates a target service request
        !modb_irqb =  onceacq & resetout
                   #  jtagacq & resetout;

"d18_sel_1 is half of the address comparator logic
        !cc_sel_1 = !sel_2              "address 0-3
                  # (adm_all & !hostack)   "assert when all selected
                  # s0          "address 0
                  # s1          "address 1
                  # s2          "address 2
                  # s3;         "address 3

"sel_2 is the first half of the address comparator logic
        !sel_2    = s4          "address 4
                  # s5          "address 5
                  # s6          "address 6
                  # s7;         "address 7

"[H,L,L,H,L,L,L,L,L,L,H,L,H,L,H]->[H,L,H,H,H,L,Z]; TEST 14 modb_irqb-td0_dso
test_vectors
([p2,p1,p0,sel2,sel1,sel0,adm_all,admreset,hostack,pc7,pc5,hostenable,pb9,admbrk,dez,pb12] ->
 [resetout,cc_sel_1,sel_2,moda_irqa,trst,modb_irqb,dez])

" ---INPUTS---                --OUTPUTS--
"                      h              d   m   m
"              a       s            r 1   o   o
"            a d h     t            e 8   d   d  
"            d m o     e   a        s _   a   b  
"            m r s     n   d        e s s _ t _  
"      s s s _ e t     a   m   p    t e e i r i
"      e e e a s a p p b p b d b    o l l r s r d
"p p p l l l l e c c c l b r e 1    u _ _ q t q e
"2 1 0 2 1 0 l t k 7 5 e 9 k z 2    t 1 2 a 1 b z
"________________________________________________
[L,L,L,L,L,L,L,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 1  reset groups
[L,L,L,L,L,L,L,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 2  sel_1 tests
[L,L,H,L,L,H,L,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 3
[L,H,L,L,H,L,L,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 4
[L,H,H,L,H,H,L,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 5

[H,L,L,H,L,L,L,L,L,H,H,L,H,L,H,X]->[H,L,L,H,H,H,Z]; "TEST 6
[H,L,H,H,L,H,L,L,L,H,H,L,H,L,H,X]->[H,L,L,H,H,H,Z]; "TEST 7
[H,H,L,H,H,L,L,L,L,H,H,L,H,L,H,X]->[H,L,L,H,H,H,Z]; "TEST 8
[H,H,H,H,H,H,L,L,L,H,H,L,H,L,H,X]->[H,L,L,H,H,H,Z]; "TEST 9
[H,H,H,L,L,L,H,L,L,H,H,L,H,L,H,X]->[H,L,H,H,H,H,Z]; "TEST 10 adm_all test

[L,L,H,L,L,H,L,L,L,H,H,L,H,H,H,X]->[H,L,H,L,H,H,Z]; "TEST 11 check moda_irqa
[L,H,L,L,H,L,L,H,L,H,H,L,H,L,H,H]->[L,L,H,H,H,H,Z]; "TEST 12 check resetout
[L,H,H,L,H,H,L,L,L,H,L,L,H,L,H,H]->[H,L,H,H,L,H,H]; "TEST 13 trst
[L,H,H,L,H,H,L,L,L,H,H,L,L,L,H,H]->[H,L,H,H,H,H,Z]; "TEST 14 trst shouldn't 
[L,H,H,L,H,H,L,L,L,H,H,L,L,L,H,L]->[H,L,H,H,H,H,Z]; "TEST 15 trst shouldn't
[H,L,H,H,L,H,L,L,L,H,H,L,L,L,L,H]->[H,L,L,H,H,L,Z]; "TEST 16 modb_irqb-from jtag
[H,L,H,H,L,H,L,L,L,H,L,L,X,L,L,L]->[H,L,L,H,H,H,L]; "TEST 17 modb_irqb-from jtag 
[H,L,H,H,L,H,L,L,L,H,H,L,X,L,L,H]->[H,L,L,H,H,L,Z]; "TEST 18 modb_irqb-from jtag
[H,L,H,H,L,H,L,L,L,L,H,L,H,L,H,L]->[H,L,L,H,H,L,Z]; "TEST 19 modb_irqb-from once
[H,L,H,H,L,H,L,L,L,H,L,L,L,L,Z,H]->[H,L,L,H,L,H,H]; "TEST 20 dez
end ucc                
