;********************************************************
;														*
;	#�@M16C Start_UP Kit�@Moniter S/W 					*
;														*
;	FILENAME: mon_main.a30								*
;	Ver		: 1.00.00									*
;	CPU		: M16C										*
;	FUNCTION: Main program for M16C Start_Up Kit(MONITER)*
;			  	(1)Define of Sections					*
;				(2)Include Header_file					*
;				(3)Inclode sub_module					*
;				(4)Define of Vector talbe				*
;	SPEC	: NOT USE at user_program					*
;				(1)NMI									*
;				(2)Address match						*
;				(3)Single step interrupt				*
;	OPTIONS	: "PDB" 0 : for HST30 use					*
;					1 : for PDB30 use					*
;			  "DBG" 0 : for Normal using				*
;					1 : for Debug of moniter program	*
;														*
;	CRAETE	: 1999.3.1									*
;	�ް�ޮ� :											*
;				V1.00.00 99/03/01 						*
;														*
; 	Copyright(c) 1995-1999 MITSUBISHI ELECTRIC Co. 		*
; 	and MITSUBISHI ELECTRIC SEMICONDUCTOR SYSTEM Co.	*
;	All Rights Reserved.								*
;														*
;********************************************************
;========================================================
;					 <Memoty Map>
;========================================================
;		0	 	-------------------------
;						SFR					(user,moniter)
;	 000400		-------------------------
;					  Internal RAM			(user)
;	 002C00		-------------------------
;					�@Internal Reserved 	(moniter)
;    004000		-------------------------
;				 Internally reserved area
;    008000		-------------------------
;					  External RAM			(Not include)
;	 0C0000		-------------------------
;				User program and fixed data	(user)
;	 0FBE00		-------------------------
;					moniter program			(moniter)
;	 100000		-------------------------
;
;========================================================
;	INCLUDE FILES
;========================================================
	.LIST		OFF
	.INCLUDE	sfr62.inc					; define of SFR
	.INCLUDE	mon30def.h				; define of MACRO
	.INCLUDE	f10.inc
	.LIST		ON
;========================================================
;	define of SECTION and Memory_map layout
;========================================================

; ----- define of Internal RAM for DEBUG -----
	.SECTION	Sdbg_ram,DATA
	.ORG		Vdbg_s
	.PAGE	'mon30dbg.h'
	.INCLUDE	mon30dbg.h
; ----- Section for RAM at moniter using -----
;	.SECTION	test,DATA
;	.ORG		1000h

	.SECTION	Smon_ram,DATA
	.ORG		Vram_s
	.PAGE	'F10RAM.a30'
	.INCLUDE	F10RAM.a30			; Define of Internal RAM for Flash memory access by moniter
	.PAGE	'Flash_h2.a30'
	.INCLUDE	Flash_h2.a30
	.PAGE	'mon30ram.h'
	.INCLUDE	mon30ram.h

; ----- Section of moniter progaran -----
	.SECTION	Smon_prg,CODE
	.ORG		Vspc_s					;
	.PAGE	'mon_spc.a30'
	.INCLUDE	mon_spc.a30				; for Special page and fixed vector process

	;.ORG		Vint_s
	.PAGE	'mon_int.a30'
	.INCLUDE	mon_int.a30				; for Interrupt program

	;.ORG		Vprg_s					;
	.PAGE	'mon_cnt.a30'
	.INCLUDE	mon_cnt.a30				; Control module of moniter
	.PAGE	'mon_cmd.a30'
	.INCLUDE	mon_cmd.a30				; Command process of moniter
	.PAGE	'mon_sub.a30'
	.INCLUDE	mon_sub.a30				; Common Subroutines of moniter program
	.INCLUDE	f_ram8.a30				;
.IF PDB==ON
	.INCLUDE	mon_cmd2.a30			; Command for PDB30
.ENDIF

;------ Interrupt vecter table at first ----------------------
;
	.SECTION 	INT_VECT_TBL,ROMDATA
	.ORG		MON_INTB +19*4
;	.ORG		MON_INTB +20*4
	.LWORD		INT_NMI					; Interrupt for transfer from UART1
	.LWORD		INT_NMI					; Interrupt for receive from UART1

; ----- Section of excution table for moniter process -----
	.SECTION	Smon_tbl,ROMDATA
	.ORG		Vtbl_s					; 0FC000H
	.PAGE	'mon_tbl.a30'
	.INCLUDE	mon_tbl.a30				; excution table for moniter process
;
; ----- Section of Vecter Table -----
	.SECTION	Smon_vec,ROMDATA
	.ORG		Vpge_s
	.page	'mon_vec.a30'
	.INCLUDE	mon_vec.a30				; Fixed Vecter table include
										; (1)Special page vecter table
										; (2)Fixed interrupt vecter table
	.END
;
;********************************************************
;														*
;	FILENAME: mon_main.a30								*
;														*
; 	Copyright(c) 1995-1999 MITSUBISHI ELECTRIC Co. 		*
; 	and MITSUBISHI ELECTRIC SEMICONDUCTOR SYSTEM Co.	*
;	All Rights Reserved.								*
;														*
;********************************************************