         DEF      MPINT:            PATCHING DEF
MPINT:   RES
         TITLE    'MULTI - PROCESSING INTERFACE MODULE'
         SYSTEM   UTS
*P*********************************************************************
*M*      MPINT - MULTIPROCESSING HARDWARE INTERFACE
*P*
*P*      NAME: MPINT
*P*      PURPOSE: TO PACKAGE ALL CPU TYPE SENSITIVE CODE INTO
*P*               A SINGLE MODULE.
*P*      DESCRIPTION: MPINT CONTAINS A NUMBER OF VERY SHORT
*P*               SUBROUTINES WHICH PERFORM FUNCTIONS WHICH
*P*               REQUIRE DIFFERENT CODE ON DEFFERENT CPU
*P*               TYPES.  ASSEMBLY SWITCHES ARE PROVIDED TO
*P*               SPECIFY WHICH VERSION OF MPINT IS CREATED.
*P*
*P*********************************************************************
         SPACE    3
SIG9     SET      1                 SELECTS SIGMA 9
560M     SET      0                 SELECTS 560
         PAGE
*
*        REGISTER DEFINITIONS
*
R0       EQU      0
R1       EQU      1
R2       EQU      2
R3       EQU      3
R4       EQU      4
R5       EQU      5
R6       EQU      6
R7       EQU      7
R8       EQU      8
R9       EQU      9
R10      EQU      10
R11      EQU      11
R12      EQU      12
R13      EQU      13
R14      EQU      14
R15      EQU      15
         PAGE
*
*        REFS/DEFS
*
         DEF      MP:SCA            SUBJECTIVE COUNTER ENABLE
         DEF      MP:SCD            SUBJECTIVE COUNTER DISABLE
         DEF      MP:MTRIG          TRIGGER MASTER CPU
         DEF      MP:LLK            LOAD INITIAL MAP AND WRITE LOCKS
         DEF      MP:HPN            READ HARDWARE CPU ADDRESS
*
*        PROCESSOR TABLES
*
         REF      S:INTBIT          INTERRUPT GROUP AND MASK
*
*        CENTRAL SUBROUTINES
*
         REF      LMA               LOAD MAP,ACCES AND LOCKS
         REF      UNMAP             GO UNMAPPED
*
*        DATA
*
         REF      C%CPU             CPU TYPE BITS
         REF      SYSTRT            SYSTEM START ADDRESS
         REF      MPIPI             INTER-PROCESSOR INTERRUPT TYPE
*
*        SREFS FOR DETERMINING WHAT KIND OF SYSGEN WAS DONE
*
         SREF     MOSTAB            * FOR MOS MEMORY
         SREF     NSCPU             * FOR MULTI-PROCESSING
         PAGE
*D*******************************************************
*D*    MP:HPN - DETERMINE CPU ADDRESS                   *
*D*                                                     *
*D*    R11 - LINK                                       *
*D*    R8 - HARDWARE ADDRESS OF CPU                     *
*D*******************************************************
MP:HPN   EQU      %
         LC       C%CPU             GET CPU TYPE
         BCS,4    HPN9              SIG9
         BCS,2    HPN560            X560
*
*
*        NOW WE HAVE A 5 OR A 7 .......
*
*        IF NSCPU > 1 WE MIGHT HAVE DUAL 7'S OR DUAL 5'S
*        AND IF ITS ON A 7 WE SHOULD HAVE PUT IN THE LMS INSTRUCTIONS
*
*        SORT IT ALL OUT
*
         BIF,S5ONLY HPN7            * IF ON A SIGMA 5...SKIP TESTS
         LI,R8    MOSTAB            * IS IT A SEVEN W/MOS?????
         BNEZ     HPNBIG7           * ***> USE THE '9' PATH
         LI,R8    NSCPU             * HOW ABOUT A MULTI-PROCESSOR ON CORE?
         BNEZ     HPNBIG7           * ***> USE THE '9' PATH, TOO
*
*        NOT NSCPU OR MOS ...... MUST BE 'OLD' SEVEN OR SIGMA 5
*
HPN7     EQU      %
         LI,R8    0                 * USE ZERO A DEFAULT PNO
         B        *R11              *
*
*        WE MUST MAKE SURE THAT I56 IS ARMED & ENABLED
*        ON SCPU'S THAT ARE SIGMA 7'S....THIS WONT
*        AFFECT MASTER 7'S (UNLESS THE HDWR IS REALLY DYING)
*
HPNBIG7  EQU      %
         LI,R8    X'0800'           * INT 56 MASK BIT
         WD,R8    X'1200'           * ARMED & ENABLED
*
*        NOW IT FALLS THRU TO 9 PATH
*
*
*        CPU NUMBER FOR THE SIGMA 9 IS DERIVED FROM THE
*        MEMORY PORT NUMBER.
*
HPN9     LCI      8                 SET CC FOR LMS
         LMS,R8   SYSTRT            ACQUIRE MEMORY STAT WD0
         MTB,+6   R11               SET COUNTER TO
         MTB,+6   R11               X'0C'
HPN9L    SCS,R8   -1                SHIFT A BIT
         MTB,-1   R11               COUNT IN REG 11
         AI,R8    0                 TEST FOR PORT BIT
         BGEZ     HPN9L             LOOP FOR ALL PORTS
         LB,R8    R11               AND RETURN IN R8
         B        *R11              RETURN
*
*        CPU NUMBER FOR THE 560 IS THE CLUSTER NUMBER
*
HPN560   RD,R8    X'10'             READ BASIC PROCESS0R
         SLS,R8   -8                RIGHT ALIGN
         B        *R11              RETURN
         PAGE
*D*******************************************************
*D*    MP:LLK - LOAD INITIAL MAP, ACCESS AND            *
*D*             WRITE LOCKS.                            *
*D*                                                     *
*D*    R0,R1,R2,R3,R4,R5,R6,R10 VOLATILE                *
*D*    R11 - LINK                                       *
*D*******************************************************
MP:LLK   EQU      %
         B        LMA               USE INITIAL VERSION
         PAGE
*D*******************************************************
*D*    MP:MTRIG - TRIGGER MASTER CPU COMMUNICATION      *
*D*               INTERRUPT.                            *
*D*                                                     *
*D*    R6,R7 - VOLATILE                                 *
*D*    R11 - LINK                                       *
*D*******************************************************
MP:MTRIG EQU      %
         LD,R6    S:INTBIT          GET GROUP AND MASK BIT
         WD,R6    X'1300',R7        ARM AND DISABLE
         WD,R6    X'1700',R7        TRIGGER EM
         WD,R6    X'1100',R7
         WD,R6    X'1300',R7        AND AGAIN
         B        *R11              RETURN TO CALLER
         PAGE
*D*******************************************************
*D*    MP:SCA - ARM AND ENABLE SUBJECTIVE COUNTER       *
*D*                                                     *
*D*    R10 - VOLATILE                                   *
*D*    R11 - LINK                                       *
*D*******************************************************
MP:SCA   EQU      %
         LI,R10   X'1040'           SELECT CLOCK 4 COUNTER
*                                   AND COUNTER EQUALS ZERO
         WD,R10   X'1200'           ARM AND ENABLE
         LW,R10   S:INTBIT
         WD,R10   X'1202'
         B        *R11              RETURN
         PAGE
*D*******************************************************
*D*    MP:SCD - DISARM SUBJECTIVE COUNTER            *
*D*                                                      *
*D*    R10 - VOLATILE                                    *
*D*    R11 - LINK                                        *
*D********************************************************
MP:SCD   EQU      %
         LI,R10   X'1040'           SELECT CLOCK 4 COUNTER
*                                   AND COUNTER EQUALS ZERO
         WD,R10   X'1100'           DISARM BOTH
         LW,R10   S:INTBIT
         WD,R10   X'1102'
         B        *R11              RETURN
         PAGE
         END

