*M*  SFAULT SLAVE HARDWARE FAULT (T46,T4C,T4D) AND PFSR RTNS
         PCC      0
MPBITS   SET      1
SFAULT:  EQU      %
         SYSTEM   UTS
         PAGE
*P*      NAME:    SFAULT
         SPACE    1
*P*      PURPOSE:
         SPACE    1
*P*               1. TO PROCESS SLAVE CPU DETECTED FAULTS FOR
*P*                  TRAPS 46,4C,4D
         SPACE    1
*P*               2. TO PERFORM THE SLAVE SPECIFIC FUNCTIONS
*P*                  FOR POWER OFF AND POWER ON INTERRUPTS/TRAPS
         SPACE    2
*P*      DESCRIPTION:
         SPACE    1
*P*          A. FOR HARDWARE FAULT TRAPS
         SPACE    1
*P*               1. UPON ENTRY FROM A T46,T4C,T4D THE ENVIRONMENT IS
*P*                  SAVED AND A REENTRANCY CHECK MADE. IF
*P*                  FAILING THE SLAVE CLIMBS INTO THE REGISTERS
*P*                  AND  WAITS. OTHERWISE IF A T4D INVALID REGISTER
*P*                  FOR A SLAVE MODE USER IS THE FAULT THEN THE
*P*                  ABORT USER LOGIC IS ENTERED IMMEDIATELY.
*P*               2. THE GENERAL HANDLING OF ALL OTHER FAULTS CONSISTS
*P*                  OF ANALYZING THE INSTRUCTION CAUSING THE TRAP AND
*P*                  FORMULATING THE ERROR LOG ENTRY IN THE BUFFER
*P*                  CONTAINED IN THE LOCAL (PRIVATE) DATA PAGE
*P*                  OF THE PARTICULAR CPU.  THEN THE FAULT TYPE
*P*                  IS TRANSLATED INTO A SPECIFIC ERROR CODE
*P*                  THE FINAL FORMULATION OF THE ERROR LOG  ENTRY
*P*                  IS PERFORMED WHERE THE ENTRIES ARE:
         SPACE    1
*P*                                 TRAP 46 - ENTRY X'2E'
*P*                                 TRAP 4C - ENTRY X'2D'
*P*                                 TRAP 4D - ENTRY X'2F'
*P*                  FOR A WD > X'2000' DETECTED IN THE INSTRUCTION
*P*                  ANALYSIS ROUTINE MOST PROCESSING IS BYPASSED
*P*                  THE PSD IS BUMPED UP AND CONTROL GOES TO PARK
*P*                  THE USER AND RETURN TO T:SIDLE.
         SPACE    1
*P*               3. THE HANDLER DECIDES THE APPROPRIATE END ACTION
*P*                  WHERE THE ULTIMATE ACTION IS TO SHUTDOWN THE SLAVE
*P*                  CPU. THE INTERMEDIATE ACTION DEPENDS ON THE
*P*                  FAULT TYPE AS FOLLOWS:
         SPACE    1
*P*               USER                  MASTER MODE
         SPACE    1
*P*      T46      ABORT USER            NONE
*P*               X'A40A'
*P*      T4C      ABORT USER
*P*               X'A40C'-BUS           SLAVE SCREECH X'2900'
*P*               X'A40E'-MAP PARITY    NONE
*P*               X'A40B'-MEM PARITY    SLAVE SCREECH X'2800'
*P*      T4D      ABORT USER            SLAVE SCREECH X'2400'
*P*               X'A40D'-INVALID REG
         SPACE    1
*P*               4. TO SHUTDOWN THE SLAVE CPU, THE HANDLER NOTIFIES
*P*                  THE MASTER  CPU AND CHANGES ITS STATE AND THEN
*P*                  CLIMBS INTO ITS REGISTERS.
*P*                  THE MASTER CPU INSURES THAT THE ERROR LOG
*P*                  BUFFER IS OUTPUT AND AN APPROPRIATE MESSAGE IS
*P*                  LOGGED ON THE OC AND INVOKES A SCREECH IF REQUIRED.
         SPACE    2
*P*          B. FOR POWEROFF AND POWERON INTERRUPTS/TRAPS
         SPACE    1
*P*               1. UPON RECEIPT OF A POWER OFF INITIAL ENTRY
*P*                  (MAPPED,INHIBITED) IS MADE TO BEGINOFF IN PFSR
*P*                  WHICH SAVES THE REGISTERS AND THEN ASCERTAINS
*P*                  THAT IT IS A SLAVE CPU.
*P*                  ALL SLAVE CPUS THEN BRANCH TO THE WAIT LOOP
*P*                  IN THIS MODULE TO AWAIT A POWER ON.
         SPACE    1
*P*               2. UPON RECEIPT OF A POWER ON INITIAL ENTRY
*P*                  (UNMAPPED,INHIBITED) IS MADE TO BEGINON IN PFSR
*P*                  WHERE THE HARDWARE ADDRESS IS USED TO
*P*                  TO SEPARATE THE MASTER AND SLAVE CPUS.
*P*                  ALL SLAVE CPUS ENTER THIS MODULE TO PERFORM THEIR
*P*                  SPECIFIC FUNCTIONS.
*P*                  AFTER DETERMINING ITS PROCESSOR INDEX, THE SLAVE
*P*                  INITIALIZATION ROUTINE IS ENTERED TO RELOAD THE
*P*                  MAP UPON RETURN A CHECK IS MADE TO INSURE THAT
*P*                  AN ENVIRONMENT IS PRESENT AND IF NOT A SLAVE
*P*                  SCREECH (X'30') IS INVOKED.  OTHERWISE, THE
*P*                  REGISTERS ARE RESTORED, THE COUNTERS
*P*                  RESET AND EXECUTION RESUMES AT THE POINT OF THE
*P*                  POWER OFF INTERRUPT/TRAP.
         PAGE
************************************************************
*                                                          *
*        REGISTER DEFINITIONS                              *
*                                                          *
************************************************************
R0       EQU      0
R1       EQU      1
R2       EQU      2
R3       EQU      3
R4       EQU      4
R5       EQU      5
R6       EQU      6
R7       EQU      7
R8       EQU      8
R9       EQU      9
R10      EQU      10
R11      EQU      11
R12      EQU      12
R13      EQU      13
R14      EQU      14
R15      EQU      15
         PAGE
************************************************************
*                                                          *
*        MODULE DEFINITIONS                                *
*                                                          *
************************************************************
         DEF      SFAULT:           MODULE BIAS
         DEF      T46ERR            ENTRY FOR TRAP 46
         DEF      T4CERR            ENTRY FOR TRAP 4C
         DEF      T4DERR            ENTRY FOR TRAP 4D
         DEF      SLVWAIT           SLAVE BAILOUT RTN
         DEF      BEGSOFF           SLAVE ENTRY FOR POWER OFF
         DEF      BEGSON            SLAVE ENTRY FOR POWER ON
         PAGE
************************************************************
*                                                          *
*        MODULE REFERENCES                                 *
*                 GLOBAL DATA CELLS                        *
*                                                          *
************************************************************
         REF      S:PNO             PROCESSOR NUMBER (INDEX)
         REF      FB:FLT            FAULT TABLE INDEXED BY PROC
         REF      S:ADR             CPU HARDWARE ADDRESS
         REF      S:CUN             CURRENT USER
         REF      F:EADDR           REAL ADDR ERRLOG BUFFER
         REF      FB:EFLG           FLAG WRD FAULT DETECTED
         REF      S:SSCRCH          SCREECH CELL (REASON,PNO)
         REF      FH:SCRCH          SCREECH REASON INDEXED BY PNO
         REF      SB:STATE          SLAVE CPU STATE TABLE
         REF      0PSD              EMPTY TSTACK FOR ROLL BACK
         REF      SB:PFLG           POST MASTER ONLY USER TABLE
         REF      SB:MPSW           SLAVE REQUEST SERVICE FLAG
         REF      SB:INIT           SLAVE INITIALIZATION FLAG TABLE
         REF      SX:SPP            PHYSICAL PAGE # OF PRIVATE  PAGE
         REF      M15               MASK
         REF      M2                MASK
         REF      M17               MASK
         REF      M24               MASK
         REF      Y008              MASK
         REF      X7F               MASK
         REF      XFC               MASK
         REF      Y8                MASK
         REF      X10               MASK
         PAGE
************************************************************
*                                                          *
*        MODULE REFERENCES                                 *
*                 LOCAL DATA CELLS                         *
*                                                          *
************************************************************
         REF      FB:CF             TRAP CC & FLOAT CONTROLS
*,*                                 FLOAT 0=T46,1=T4C,2=T4D
         REF      F:TEMP1           TEMP CELL
         REF      F:TEMP2           TEMP CELL
         REF      FD:PSD            PSD AT TIME OF FAULT
         REF      F:REGS            REGS AT TIME OF FAULT
         REF      FB:END            SPECIFIC FAULT REASON
         REF      F:INST            INSTRUCTION AT TRAP LOC
         REF      F:IREAL           REAL ADDR OF INST
         REF      F:EVIRT           ANLZ CC AND VIRT ADDR
         REF      F:EREAL           EFFECTIVE ADDRESS
         REF      FH:IFLG           FLAGS & CC FOR ERRLOG BUF
         REF      F:STBL            FAULT AREA START IN PRIVATE PAGE
         REF      FD:EPSD           PSD IN ERRLOG BUFFER
         REF      F:ELOGB           START OF ERRLOG BUFFER
         REF      F:BREG            X560 LAST BRANCH REGISTER
         REF      PSD%T46           PSD FOR 46
         REF      J:JIT             THE JIT
         REF      J:RNST            RUN STATUS FOR USER
         REF      J:ABC             ABORT CODE FIELD
         REF      JX:CMAP           * FOR FIGURING OUT WHERE FAULT STATUS
         REF      ERO               ERROR CODE FIELD
*
         REF      OFFCNTER          COUNT OF POWEROFFS
         REF      ONCNTER           COUNT OF POWERONS
         REF      BALANCE           ENVIRON PRESENT FLAG FOR PFSR RTNS
         REF      NFRST             FLAG FOR MULTIPLE POWEROFFS
         REF      POWROFF           PSD FOR POWER OFF
         REF      SREGS             REG BLOCK 0 AT POWER OFF
         REF      SREGS1            REG BLOCK 1 AT POWER OFF
         PAGE
************************************************************
*                                                          *
*        MODULE REFERENCES                                 *
*                 ROUTINES                                 *
*                                                          *
************************************************************
         REF      T:SIDLE           SLAVE IDLE LOOP
         REF      T:SAVE            SAVE ENVIRON RTN
*
         REF      T:PFRET           REINITIALIZE SLAVE ENVIRONMENT
         REF      PFSCR             EXIT FOR PFSR TYPE SCREECH
         REF      Y1                DATA OF X'10000000'
         REF      ERRLOG            ERROR LOGGING ROUTINE
POLLBUF  EQU      FD:EPSD+2         PLACE TO STICK 560 POLR STATUS
         REF      C%CPU             CPU TYPE CELL
         PAGE
************************************************************
*                                                          *
*        START OF MODULE                                   *
*                 DATA AND VARIABLES                       *
*                                                          *
************************************************************
FIP      EQU      1                 PARITY ERROR FETCHING INST
IAP      EQU      2                 PARITY ERROR INDRECT ADDRESS
NOPE     EQU      X'C'              CCS RESET(LMS) NO PARITY ERRORS
A4D      EQU      2                 4D CODE INDEX
RP1      EQU      X10               RP1 BLOCK
*
*
*
         BOUND    8
PSD1     :PSD     (IA,REENT),(INH),(MAP)  FOR SLAVE CPU
PSD2     :PSD     (IA,CLRPDF),(INH),(MAP) * SLAVE WILL RE-ARM 56 ON SIG7
DEPSD    :PSD     (IA,CLEAR),(INH),(MAP)   TO CLEAR POWERON INTERRUPT
6C6D     DATA     X'6C',X'6D'
         PAGE
*F*      NAME:    T46ERR
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               INITIAL ENTRY FOR TRAP 46 (WATCHDOG) TO CHECK
*F*               FOR PHASE 1 TIMEOUT
         SPACE    1
*F*      DESCRIPTION:
         SPACE    1
*F*               IF A PHASE 1 TIMEOUT HAS BEEN REPORTED AN IMMEDIATE
*F*               RETURN IS EFFECTED. OTHERWISE CONTROL FALLS
*F*               DIRECTLY INTO THE REENTRANCY ROUTINE
*F*               (T4CERR,T4DERR)
         SPACE    3
*F*      NAME:    T4CERR,T4DERR
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO PERFORM THE INITIAL SAVING OF THE ENVIRONMENT
*F*               AND TO INSURE THAT THE HANDLER HAS NOT BEEN
*F*               REENTERED DURING THE PROCESSING OF A FAULT.
         SPACE    3
*D*      NAME:    T4CERR,T4DERR
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               ALL REGISTERS ARE SAVED
         SPACE    1
*D*      CALL:
         SPACE    1
*D*               UPON RECEIPT OF A TRAP 46 (NOT PHASE 1) AND
*D*               TRAP 4C AND 4D.
         SPACE    1
*D*      ENVIRONMENT:
         SPACE    1
*D*               MAPPED,MASTER MODE, INHIBITED, RUNS WITH PDF ON
*D*               UNTIL INITIAL TESTS ARE PERFORMED.
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               PSD%T46 - BEGINNING OF ORDERED GROUP OF PSDS
         SPACE    3
*D*      OUTPUT:
         SPACE    1
*D*               FB:CF - CCS AND FLOAT CONTROLS AT TIME OF TRAP
*D*                         WHERE FLOAT CONTROL SIGNIFY:
*D*                                 0 = T46
*D*                                 1 = T4C
*D*                                 2 = T4D
*D*               FB:FLT - VALUE FROM FLOAT CONTROLS EXCEPT
*D*                        WHEN INVALID REGISTER FOR T4D SLAVE MODE
*D*                        DETECTED THEN FB:FLT = 0.
*D*               FD:PSD - PSD AT TIME OF TRAP
*D*               F:REGS - REGISTERS AT TIME OF TRAP
*D:               F:BREG - CONTENTS OF LAST BRANCH REGISTER ON X560
         SPACE    3
*D*      DESCRIPTION:
         SPACE    1
*D*               1. UPON ENTRY THE CONDITION CODES AND FLOAT CONTROLS
*D*                  ARE STORED IN FB:CF. THE CONTENTS OF THE LAST
*D*                  BRANCH REGISTER ON X560 OR -1 SIGMA 9 IS STORED
*D*                  IN F:BREG. IF THE FB:FLT ENTRY
*D*                  IS NON-ZERO, INDICATING THE HANDLER HAS BEEN
*D*                  REENTERED, CONTROL IS IMMEDIATELY DIVERTED
*D*                  TO WAIT IN THE REGISTERS.
         SPACE    1
*D*               2. OTHERWISE THE FLOAT CONTROLS VALUE IS USED AS
*D*                  THE FB:FLT ENTRY AND WHEN CONVERTED IS USED TO
*D*                  FETCH THE APPROPRIATE PSD WHICH IS STORED
*D*                  IN FD:PSD.
         SPACE    1
*D*               3. THE PDF IS THEN CLEARED AND THE REGISTERS SAVED
         SPACE    1
*D*               4. A TEST IS MADE TO DETERMINE IF THE FAULT IS
*D*                  INVALID REGISTER 4D FOR A SLAVE MODE USER
*D*                  AND IF SO CONTROL IS TRANSFERRED TO THE ABORT
*D*                  USER LOGIC AFTER ZEROING OUT THE FB:FLT ENTRY
*D*                  OTHERWISE CONTROL FALLS THROUGH TO PROFLT
         PAGE
************************************************************
*                                                          *
*        HARDWARE FAULT ENTRIES                            *
*                                                          *
************************************************************
         LPSD,1   PSD%T46           YES,RETURN CLEAR PDF
T46ERR   BCS,8    %-1               PHASE 1 TIMEOUT ?
T4DERR   EQU      %
T4CERR   EQU      %
         STCF     FB:CF             SAVE CC&FLOAT CONTROLS
         STW,R2   F:TEMP2           SAVE TEMP REGS
FRTN2    STW,R3   F:TEMP1
         BIF,S7S9 FRTN3             * ONLY FOR X560'S....ELSE AROUND
         LI,R3    -1
         RD,R3    X'031D'           GET LAST BRANCH REGISTER FOR X560
         STW,R3   F:BREG            SAVE IT
FRTN3    EQU      %
         LW,R3    S:PNO             GET PROCESSOR #
         MTB,0    FB:FLT,R3         PROCESSING FAULT
         BNEZ     WAITIN            YES,REENTERED
         LB,R2    FB:CF             NOW WHAT TYPE PROCESSING
         AND,R2   M2
         STB,R2   FB:FLT,R3         SAVE TYPE
         SLS,R2   1
         LD,R2    PSD%T46,R2        GET PSD
         STD,R2   FD:PSD            AND SAVE
         LW,R2    F:TEMP2
         LW,R3    F:TEMP1
         LPSD,1   PSD2              * CLEAR PDF HERE
CLRPDF   EQU      %
         LPSD,3   PSD1              * GET PSD, CLEAR I56(IF HERE)
REENT    STM,R0   F:REGS            SAVE REGS
         LB,R2    FB:CF
         CI,R2    X'12'             4D INVALID INSTRUCTION
         BNE      PROFLT            NO
         LW,R2    Y008
         CW,R2    FD:PSD            MASTER MODE
         BAZ      PROFLT            YES
         LI,R12   A4D               T4D USER CODE
         STB,R12  FB:END            SET ERROR CODE
         B        AB1               BYPASS PROCESSING
         PAGE
*F*      NAME:    PROFLT
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO CONTROL THE FLOW OF THE FAULT HANDLING LOGIC
         SPACE    3
*F*      DESCRIPTION:
         SPACE    1
*F*               THIS IS A SERIES OF CALLS TO THE VARIOUS ROUTINES FOR
*F*               PROCESSING THE HARDWARE FAULT
         SPACE    1
*F*               1. ANAL - TO ANALYZE THE INSTRUCTION CAUSING THE TRAP
*F*               2. ERRFIX - TO TRANSLATE THE FAULT TYPE INTO AN ERROR
*F*                           CODE INDEX
*F*               3. LOGPRIM - TO FINALIZE THE FORMULATION OF THE ERROR
*F*                            LOG ENTRY CREATED BY ANAL
*F*               RETURN FROM THE LAST ROUTINE CAUSES CONTROL TO
*F*               FALL INTO THE ENDACT ROUTINE
         PAGE
************************************************************
*                                                          *
*        PROCESS FAULT                                     *
*                                                          *
************************************************************
PROFLT   EQU      %
         BAL,R15  ANAL              ANALYZE INSTRUCTION
         BAL,R15  ERRFIX            CONVERT TO ERROR CODE INDEX
         BAL,R15  LOGPRIM           LOG PRIMARY FAULT
         PAGE
*F*      NAME:    ENDACT
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO DETERMINE THE DISPOSITION OF THE FAULT HANDLING
         SPACE    1
*F*      DESCRIPTION:
         SPACE    1
*F*               THIS ROUTINE CONTAINS THE ROUTINES:
*F*                    AB1 - TO ABORT THE USER
*F*                    SCREECH - PREPARE TO INVOKE SLAVE SCREECH
*F*                    FINAL - NOTIFICATION OF MASTER CPU
*F*                    SLVWAIT - BAILOUT POINT FOR ANY ROUTINE
*F*                              WHEN SLAVE HAS GOTTEN INTO MASTER CODE
         SPACE    3
*D*      NAME:    ENDACT
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               ALL REGISTERS ARE VOLATILE
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               FD:PSD - PSD AT TIME OF TRAP
*D*               FB:END - ERROR CODE INDEX
*D*               S:PNO - PROCESSOR INDEX
*D*               S:CUN - CURRENT USER
*D*               F:REGS - REGISTERS AT TIME OF TRAP
         SPACE    2
*D*      OUTPUT:
         SPACE    1
*D*        FOR AB1 (ABORT USER)
*D*               J:RNST - X'80' BIT SET I.E. ERROR USER
*D*               J:ABC - X'A4'
*D*               ERO - ERROR SUBCODE
*D*                       X'A' - WATCHDOG
*D*                       X'D' - INSTRUCTION EXCEPTION
*D*                       X'C' - BUS CHECK
*D*                       X'E' - MAP PARITY
*D*                       X'B' - MEMORY PARITY
*D*               SB:PFLG - MASTER ONLY FLAG FOR USER SET
         SPACE    1
*D*        FOR AB1 (CONTINUE USER WD >X'2000')
*D*               FB:FLT = 0
*D*               NO ERROR CODE SET
*D*               FD:PSD INCREMENTED BY 1
         SPACE    1
*D*        FOR SCREECH (INVOKE SLAVE SCREECH)
*D*               FH:SCRCH - SPECIFIC SCREECH CODE
*D*                          SAME AS LEFT HALFWORD OF
*D*                          S:SSCRCH IF NO OTHER SLAVE INVOKING
*D*                          SCREECH AT THE SAME TIME
         SPACE    1
*D*        FOR FINAL
*D*               FB:EFLG - VALUE FROM FB:END
*D*               SB:STATE - 0
*D*               SB:INIT - RESET START BIT SET STOP BIT
*D*               SB:MPSW - SLAVE REQUEST SERVICE FLAG SET
*D*               S:SSCRCH - EITHER ZERO OR THE SCREECH CODE
*D*                          IN THE FORM (REASON,S:PNO) OR IF
*D*                          ORIGINALLY NON-ZERO REMAINS
*D*                          AS PREVIOUSLY SET
         SPACE    3
*D*      DESCRIPTION:
         SPACE    1
*D*               AN INITIAL CHECK OF THE MASTER/SLAVE BIT OF THE
*D*               PSD AT THE TIME OF THE TRAP CAUSES CONTROL
*D*               TO GO TO AB1 TO ABORT THE USER OR TO SCREECH FOR
*D*               POSSIBLE INVOCATION OF A SLAVE SCREECH
         SPACE    1
*D*        AB1
*D*               IF NO CURRENT USER (S:CUN) IS PRESENT OR THE TSTACK
*D*               IS DEEMED INVALID EXIT IS MADE TO FINAL RTN
*D*               OTHERWISE IF ROOM FOR TWO ENVIRONMENTS IS NOT
*D*               AVAILABLE IN THE STACK IT IS ROLLED BACK AND THE
*D*               USER'S ENVIRONMENT IS SAVED VIA A CALL TO T:SAVE
*D*               IF F:ELOGB IS <0 INDICATING A WD >X'2000'
*D*               THEN CONTROL JUMPS TO AB3 WHERE THE FB:FLT ENTRY IS
*D*               RESET AND THE SLAVE EXITS TO T:SIDLE
*D*               UPON RETURN J:RNST (X'80') IS SET INDICATING AN
*D*               ERROR CONDITION. THE MAJOR CODE (X'A4')
*D*               IS STORED IN J:ABC AND THE APPROPRIATE SUBCODE
*D*               IS STORED IN ERO.
*D*               THE MASTER ONLY FLAG IS SET (SB:PFLG) AND IF
*D*               THE T4D INVALID INSTRUCTION IS THE ERROR THEN THE
*D*               SLAVE EXITS TO T:SIDLE
*D*               OTHERWISE CONTROL IS TRANSFERRED TO FINAL RTN.
         PAGE
************************************************************
*                                                          *
*        END ACTION                                        *
*                                                          *
************************************************************
ENDACT   LW,R9    Y008
         CW,R9    FD:PSD            MASTER MODE
         BAZ      SCREECH           YES,SCREECH
AB1      MTW,0    S:CUN             ANY CURRENT USER
         BEZ      FINAL0            NO
         LW,R1    TSTACK            OK STACK
         BLEZ     FINAL0            NO
         LH,R1    TSTACK+1          GET SPACE AVAILABLE
         AND,R1   M15
         CI,R1    42                ROOM
         BGE      AB2               YES
         LD,R0    0PSD
         STD,R0   TSTACK            MAKE ROOM
AB2      LCI      0
         LM,R0    F:REGS
         PUSH     6,R13
         LD,R0    FD:PSD
         BAL,R2   T:SAVE            SAVE ENVIRONMENT
         LW,R1    S:PNO             GET PROCESSOR INDEX
         LW,R6    F:ELOGB           GET ERRLOG BUFFER AS FLAG
         BLZ      AB3               WRITE DIRECT >X'2000'
         LB,R3    FB:END
         LW,R5    Y8                GET MASK
         STS,R5   J:RNST            SET ERROR USER BIT
         LI,R4    X'A4'
         STB,R4   J:ABC             MAJOR CODE
         LI,R5    X'FF'
         LB,R4    ABCODE,R3         GET SUBCODE
         STS,R4   J:JIT+ERO
         STB,R1   SB:PFLG,R1        SET MASTER ONLY FLAG FOR USER
         CI,R4    X'B'              * WAS IT MEM FLT?
         BE       SCREECH           * MAKE SURE TO SCREECH
         CI,R4    X'D'              INTRUCTION EXCEPTION
         BNE      FINAL0            NO,TO SHUTDOWN
AB3      LI,R5    0
         STB,R5   FB:FLT,R1         ZERO OUT FAULT
         B        T:SIDLE           YES, BACK TO IDLE
*
*
ABCODE   DATA,1   0,X'A',X'D',X'C',X'E',X'B'  0,WD,INST,BUS,MAP,MEM
         BOUND    4
         PAGE
*D*      SCREECH
         SPACE    1
*D*               THE VALUE IN FB:END IS USED AS AN INDEX INTO
*D*               A TABLE OF SCREECH CODES.  IF THE ENTRY IS ZERO
*D*               INDICATING THAT NO SCREECH IS TO BE INVOKED, CONTROL
*D*               IS TRANSFERRED TO THE FINAL RTN
         SPACE    1
*D*               OTHERWISE THE CODE IS SAVED IN THE FH:SCRCH ENTRY
*D*               FOR THE PROCESSOR AND IS MERGED WITH THE VALUE IN
*D*               S:PNO AND CARRIED IN R15 INTO THE FINAL RTN
         SPACE    1
*D*               THE POSSIBLE SCREECH CODES
*D*                      X'2400' - INSTRUCTION EXCEPTION
*D*                      X'2900' - BUS CHECK
*D*                      X'2800' - MEMORY PARITY
         PAGE
SCREECH  EQU      %
         LB,R1    FB:END
         LH,R15   SCODE,R1
         BEZ      FINAL             NO SCREECH JUST SHUTDOWN
         LW,R1    S:PNO             PROCESSOR NUMBER
         STH,R15  FH:SCRCH,R1       SAVE SPECIFIC CODE
         SLS,R15  16
         AW,R15   S:PNO
         B        FINAL
*
*
*
SCODE    EQU      %
         DATA,2   0,0,X'2400',0,X'2900',X'2800'
*                                   INVALID,WDOG,INST EXCPT,MAP,BUS,MEM
         BOUND    4
         PAGE
*D*      FINAL
         SPACE    1
*D*               UPON ENTRY R15 CONTAINS EITHER THE SCREECH CODE OR 0
*D*               THE VALUE IN FB:END IS USED AS A FLAG TO BE SET IN
*D*               FB:EFLG TO NOTIFY THE MASTER THAT A SLAVE HARDWARE
*D*               FAULT HAS OCCURED
         SPACE    1
*D*               THE SLAVE SETS ITS STATE TO STOPPED (SB:STATE=0)
*D*               THEN RESETS THE START BIT AND SETS THE STOP BIT
*D*               IN SB:INIT. THEN IT SETS THE SLAVE REQUEST SERVICE
*D*               FLAG (SB:MPSW) AND STORES THE CONTENTS OF R15 IN
*D*               S:SSCRCH UNLESS THE PREVIOUS VALUE IN IT WAS NON-ZERO
*D*               CONTROL FALLS THROUGH INTO THE WAITIN ROUTINE
         SPACE    3
*D*      WAITIN
         SPACE    1
*D*               AT WAITIN THE REAL ADDRESS OF THE START OF THE
*D*               FAULT LOCAL DATA AREA IN THE PRIVATE PAGE IS LOADED
*D*               INTO R7 AND CONTROL PASSES TO SLVWAIT
         PAGE
*F*      NAME:    SLVWAIT
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO PROVIDE A BAILOUT POINT FOR SLAVE CPUS THAT
*F*               HAVE GOTTEN INTO MASTER CPU CODE IN
*F*               SITUATIONS THAT INDICATE THAT CPU HAS
*F*               BEEN STOPPED IN TERMS OF SOFTWARE
*F*               BUT NOT TAKEN OUT OF RUN ( I.E., CPU IS
*F*               EXECUTING UNMAPPED CODE)
         SPACE    2
*D*      SLVWAIT
         SPACE    1
*D*               SLVWAIT IS BAL'ED TO ON R11 WHICH IS SAVED
*D*               IN F:TEMP1, PROBABLY IN MASTER COPY
*D*               R5 AND R6 ARE LOADED WITH A TWO INSTRUCTION
*D*               LOOP, THE ALARM IS SOUNDED AND THE CPU
*D*               BRANCHES TO R5.
         PAGE
FINAL0   LI,R15   0                 ENTRY FOR NO SCREECH
FINAL    EQU      %
         LW,R1    S:PNO
         LB,R3    FB:END            GET ERROR INDEX
         STB,R3   FB:EFLG,R1        USE AS FLAG FOR MASTER
         LI,R3    0
         STB,R3   SB:STATE,R1       SET STATE TO STOPPED
         LB,R3    SB:INIT,R1        GET INITIALIZATION FLAGS
         AND,R3   XFC               RESET START &STOP
         AI,R3    STOPBIT           SET STOP BIT
         STB,R3   SB:INIT,R1
         STB,R3   SB:MPSW,R1        SET SLAVE REQUEST SERVICE
         XW,R15   S:SSCRCH          STORE SCREECH
         BEZ      %+2               PREVIOUSLY SET
         STW,R15  S:SSCRCH          YES RESTORE PREVIOUS
************************************************************
*        WAIT IN REGISTERS ROUTINE                         *
************************************************************
WAITIN   EQU      %
         LI,R7    F:STBL            START OF FAULT AREA IN PRIVATE PAGE
         BIF,S7   SIG7LRA1          * SIMULATE LOAD REAL ADDRESS(LRA)
         LCI      8                 GET REAL ADDRESS
         LRA,R7   R7
         B        DIELOOP           * SKIP SIMULATED 7 INTRUCTION
*
*
SIG7LRA1 EQU      %
         CI,R7    X'8000'           * IF BELOW...MUST BE 1-1 MAPPED
         BL       DIELOOP           * SO ADDRESS IS O.K.
         LW,R6    R7                * SET UP THE REGISTERS.....
         SLD,R6   -9                * TO BUILD THE ADDRESS
         LOAD,R6  JX:CMAP,R6        * BASED ON WHATS IN THE JIT
         SLD,R6   9                 * NOW MERGE OFFSET BACK IN
         LW,R7    R6                * NOW IT'S O.K.!
*
*
DIELOOP  EQU      %
         LI,R11   SLVWAIT
SLVWAIT  STW,R11  F:TEMP1           SAVE LINK
         LW,R5    WALOOP            LOAD REGISTERS
         LW,R6    WAREG
         WD,0     X'41'             SOUND THE ALARM
WAREG    B        R5                CLIMB INTO REGISTERS
WALOOP   WAIT
         PAGE
*F*      NAME:    ANAL
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO ANALYZE THE INSTRUCTION CAUSING THE TRAP
*F*               AND TO FORMULATE THE ERROR LOG ENTRY FROM THE
*F*               DATA GENERATED
         SPACE    1
*D*      NAME:    ANAL
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               R15 = LINK REGISTER
*D*               ALL OTHERS VOLATILE
         SPACE    1
*D*      CALL:
         SPACE    1
*D*               FROM THE PROFLT DRIVER
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               FD:PSD - PSD AT TIME OF TRAP
         SPACE    1
*D*      OUTPUT:
         SPACE    1
*D*               F:ELOGB - DATA COLLECTED FROM ANALYSIS OF INSTRUCTION
*D*                         IN ERROR LOG FORMAT
*D*               FD:EPSD - PSD AT TIME OF TRAP
*D*               F:IREAL - REAL ADDRESS OF INSTRUCTION
*D*               FH:IFLG - BYTE 0 TRAP CC AND FLOAT CONTROLS
*D*                         BYTE 1 BIT 7 FIP PE FETCHING INST
*D*                                BIT 6 IAP PE GOING INDIRECT
*D*               F:INST - INSTRUCTION CAUSING TRAP
*D*               F:EVIRT - BYTE 0 - CCS FROM ANLZ INSTRUCTION
*D*                         BYTE 1-3 EFFECTIVE ADDRESS
*D*               F:EREAL - REAL EFFECTIVE ADDRESS
         SPACE    2
*D*      DESCRIPTION:
         SPACE    1
*D*               UPON ENTRY THE ERROR LOG BUFFER IN THE PRIVATE PAGE
*D*               IS ZEROED OUT.  THE PSD AT THE TIME OF THE TRAP
*D*               IS FETCHED AND STORED IN FD:EPSD AND THE ADDRESS
*D*               CONVERTED TO THE REAL ADDRESS AND STORED IN F:IREAL
*D*               THE INSTRUCTION AT THAT LOCATION IS FETCHED AND STORED
*D*               IN F:INST AND IF A PARITY ERROR IS DETECTED THE FIP
*D*               BIT IS SET AND THE ROUTINE IS EXITED. OTHERWISE THE
*D*               INSTRUCTION IS EXAMINED AND IF INDIRECT ADDRESSING IS
*D*               SPECIFIED THE REAL ADDRESS AND CONTENTS ARE FETCHED
*D*               TO INSURE NO PARITY ERROR WILL BE ENCOUNTERED WHEN
*D*               LATER ANLZING THE INSTRUCTION. IF ONE IS DETECTED
*D*               THE IAP FLAG IS SET AND THE ROUTINE IS EXITED
         SPACE    1
*D*               THE ENVIRONMENT AT THE TIME OF THE TRAP IS RESTORED
*D*               AND THE INSTRUCTION IS ANLZ'ED THE CONDITION CODES
*D*               AND EFFECTIVE ADDRESS ARE STORED IN F:EVIRT
*D*               IF THE INSTRUCTION IS  AN IMMEDIATE TYPE
*D*               THE ROUTINE EXITS OTHERWISE THE REAL
*D*               EFFECTIVE ADDRESS IS OBTAINED AND STORED IN F:EREAL
*D*               IF THE INSTRUCTION IS AN EXU THEN THE WHOLE
*D*               OPERATION IS REPEATED. OTHERWISE, A CHECK IS MADE
*D*               TO SEE IF THE INST. IS A WD >X'2000' IF NOT
*D*               THE ROUTINE EXITS. IF IT IS THE INSTRUCTION ADDRESS
*D*               OF THE SAVED PSD (FD:PSD) IS INCREMENTED BY 1 AND
*D*               A -1 IS SET IN THE 1ST WORD OF F:ELOGB AS A FLAG
*D*               CONTROL IS TRANSFERRED TO AB1 TO PARK THE USER
*D*               FOR RESCHEDULING AND RETURN TO T:SIDLE.
         PAGE
************************************************************
*                                                          *
*        ANALYZE INSTRUCTION                               *
*                                                          *
************************************************************
ANAL     EQU      %
         LI,R1    0                 ZERO OUT ERROR LOG BUFFER
         LI,R2    -10
         STW,R1   F:ELOGB+10,R2
         BIR,R2   %-1
         LD,R0    FD:PSD            GET PSD AT TIME OF TRAP
         STD,R0   FD:EPSD           PUT IN ERROR LOG BUFFER
         AND,R0   M17               STRIP ADDRESS
AN1      EQU      %
         BAL,R13  GETREAL           GET REAL ADDR OF INST
         STW,R2   F:IREAL           SAVE IREAL ADDRESS OF INST
         BAL,R13  GCONT             GET CONTENTS OF LOC
         STW,R0   F:INST            SAVE INST
         BCR,NOPE AN2               ANY ERRORS FETCHING
         MTH,FIP  FH:IFLG           YES SET FLAG
         B        *R15              RETURN
AN2      AI,R0    0                 CHECK INST FOR INDIRECT
         BGEZ     AN3               NOT INDIRECT
         AND,R0   M17               YEP GO SEE IF CAN FETCH
         BAL,R13  GCONT
         BCR,NOPE AN3               NO ERROR
         MTW,IAP  FH:IFLG           IAP=2
         B        *R15
AN3      STW,R15  F:TEMP1           SAVE RETURN
         STW,R1   F:TEMP2           AND MAPPED WORD
AN4      LCI      0
         LM,R0    F:REGS            GET USERS REGS
         ANLZ,R0  F:INST            ANALYZE INSTRUCTION
         STCF     R0                SAVE CC
AN5      STW,R0   F:EVIRT
         LW,R1    F:TEMP2
         LCF      R0
         BCS,1    *F:TEMP1          IMMEDIATE INST GET OUT
         BAL,R13  GETREAL1          CCS SET FROM LCF
         STW,R2   F:EREAL           REAL EFFECTIVE ADDRESS
         LB,R0    F:INST
         AND,R0   X7F
         CI,R0    X'67'             WAS INST AN EXU
         BNE      AN6               CHECK FOR WD >X'2000'
         LW,R0    F:EVIRT           YES GO DO AGAIN
         LW,R15   F:TEMP1
         B        AN1
AN6      CLM,R0   6C6D              IS IT WD
         BCS,9    *F:TEMP1          NO
         INT,R13  F:EVIRT           CHECK MODE
         CI,R13   X'2000'
         BL       *F:TEMP1          NOT EXTERNAL MODE
         MTW,1    FD:PSD            BUMP UP PSD
         LI,R13   -1
         STW,R13  F:ELOGB           USE AS FLAG
         B        AB1               BYPASS REMAINDER OF PROCESSING
*
GETREAL  LCI      8                 GET PHYSICAL ADDRESS
GETREAL1 EQU      %
         STCF     R3                * SAVE ANLZ CC'S
         BIF,S7   SIG7LRA2          * SIMULATE THE LRA INSTRUCTION
         LC       R3                * GET THE CC'S BACK
         LRA,R7   R0                *
ANDIT    EQU      %                 *
         AND,R2   M24
         B        *R13
SIG7LRA2 EQU      %
         LW,R2    R0                * WHERE WAS I SUPPOSED TO LRA FROM?
         CI,R0    X'8000'           * BELOW OVERLAYS ?
         BL       ANDIT             * I GUESS NOT
         SLS,R3   -30               * SHIFT CC'S
         LCW,R3   3                 * AND DONT IGNORE SIGN EXTENSION
         LW,R4    R0                * GET R0 INTO R4
         SLD,R4   -9                * EASE OFF OFFSET
         LOAD,R4  JX:CMAP,R4        * GET THE VALUE FROM THE JIT
         SLD,R4   9+2               * SHIFT IT BACK
         SLD,R4   *R3               * DEPENDING ON ADDRESSING TYPE
         LW,R2    R4                * PUT ME IN THE RIGHT REGISTER
         B        ANDIT             * AND FOLLOW THE FLOW
*
GCONT    EQU      %
         BIF,S7   GCONTS7           * IN CASE OF 7, LMS W/CC=1 IS NO-NO
         LCI      X'1'              * SET UP LMS
         LMS,R0   *R0
         B        *R13
*
*        READ-AND-INHIBIT PARITY ROUTINE FOR SIGMA 7'S
*
GCONTS7  EQU      %
         LI,R1    X'0800'           * MASK BIT FOR I56
         WD,R1    X'1100'           * TO DISABLE
         RD,R2    X'0010'           * READ AND RESET MFI LIGHTS
         LW,R0    *R0               * GET THE CONTENTS
         RD,R2    X'0010'           * READ AND RESET MFI LIGHTS
         WD,R1    X'1200'           * RE-ARM I56
         CI,R2    0                 * DID WE FAULT ON THE FETCH?
         BEZ      *R13              * NOPE, RETURN W/CC'S=0
         LCI      X'1'              * YEP, SET CC'S AS IF LMS USED
         B        *R13              * AND RETURN
         PAGE
*F*      NAME:    ERRFIX
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO TRANSLATE THE FAULT TYPE INTO AN ERROR CODE INDEX
         SPACE    1
*D*      NAME:    ERRFIX
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               R15 = LINK REGISTER
*D*               ALL OTHER REGISTERS ARE VOLATILE
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               FB:FLT - GENERAL FAULT TYPE
*D*                                 0 - T46
*D*                                 1 = T4C
*D*                                 2 = T4D
*D*               FB:CF = TRAP CC AND FLOAT CONTROLS
         SPACE    1
*D*               FB:END = INDEX FOR ERROR CODES
*D*                                 1 = T46 WATCHDOG
*D*                                 2 = T4D INSTRUCTION EXCEPTION
*D*                                 3 = T4C MAP PARITY
*D*                                 4 = T4C BUS CHECK
*D*                                 5 = MEMORY PARITY
         SPACE    1
*D*      DESCRIPTION:
         SPACE    1
*D*               THE VALUE IN FB:FLT IS USED AS AN INDEX INTO A TABLE
*D*               TO CONVERT THE GENERAL FAULT TYPE TO AN ERROR CODE
*D*               INDEX. FOR T4C THE CONDITION CODES FROM FB:CF
*D*               ARE USED AS A SECONDARY INDEX FOR THE PARTICULAR
*D*               TYPE OF MEMORY FAULT DETECTED
*D*               AFTER STORING IN FB:END THE ROUTINE EXITS
         PAGE
************************************************************
*                                                          *
*        ERRFIX ROUTINES                                   *
*                                                          *
************************************************************
ERRFIX   EQU      %
         LW,R1    S:PNO
         LB,R2    FB:FLT,R1         GET FAULT TYPE
         LB,R12   ACODES,R2         GET ERROR CODE INDEX
         BEZ      T4CFX             IS T4C TYPE
RBEND    STB,R12  FB:END            SAVE THE VALUE
         B        *R15              RETURN
*
T4CFX    LB,R2    FB:CF             GET CONDITION CODES
         SLS,R2   -5                POSITION THEM
         LB,R12   4CODES,R2         GET SPECIFIC TYPE OF T4C
         B        RBEND
*
*
*
ACODES   DATA,1   1,0,2,0           WDOG,4C,4D,0
4CODES   DATA,1   5,3,4,5           MEM,MAP,BUS,MEMORY
         BOUND    4
         PAGE
*F*      NAME:    LOGPRIM
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO FINISH FORMULATING THE ERROR LOG ENTRY
         SPACE    4
*D*      NAME:    LOGPRIM
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               R15 = LINK REGISTER
*D*               ALL OTHER REGISTERS ARE VOLATILE
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               ALL DATA COLLECTED IN THE ERROR LOG BUFFER
*D*               FB:CF = TRAP CC AND FLOAT CONTROLS
*D*               S:PNO = PROCESSOR INDEX
*D*               FB:FLT = GENERAL FAULT TYPE
*D*               S:ADR = CPU HARDWARE ADDRESS TABLE
         SPACE    1
*D*      OUTPUT:
         SPACE    1
*D*               F:ELOGB = WORD 0 OF ERROR LOG BUFFER CONTAINING
*D*                         CODE COUNT AND CPU ADDRESS
*D*                         WHERE CODE IS
*D*                                 X'2E' - T46
*D*                                 X'2D' - T4C
*D*                                 X'2F' - T4D
*D*               FH:IFLG = BYTE 0 CONTAINS VALUE FROM FB:CF
*D*               F:EADDR = REAL ADDRESS OF ERROR LOG BUFFER
         SPACE    3
*D*      DESCRIPTION:
         SPACE    1
*D*               UPON ENTRY THE FAULT TYPE (FB:FLT) IS USED
*D*               TO SELECT THE APPROPRIATE ERROR LOG ENTRY CODE
*D*               WHICH IS MERGED WITH THE CPU HARDWARE ADDRESS
*D*               AND STORED IN F:ELOGB.
*D*               THE TRAP CCS AND FLOAT CONTROLS FROM FB:CF ARE
*D*               STORED IN BYTE 0 OF FH:IFLG AND THE REAL ADDRESS
*D*               OF THE ERROR LOG BUFFER IS OBTAINED AND
*D*               STORED IN THE F:EADDR ENTRY FOR THE PROCESSOR
*D*               THE ROUTINE EXITS
         PAGE
************************************************************
*                                                          *
*        LOG PRIMARY ERROR                                 *
*                                                          *
************************************************************
LOGPRIM  LW,R1    S:PNO
         LB,R2    FB:FLT,R1         GET FAULT TYPE
         LH,R2    ETYPE,R2          GET CODE COUNT FIELDS
         LW,R3    S:ADR,R1          GET CPU ADDRESS
         STH,R2   R3                MERGE THEM
         STW,R3   F:ELOGB           STORE IN BUFFER
         LB,R3    FB:CF             GET TRAP CCS AND FLOAT CONTROLS
         STB,R3   FH:IFLG           STORE IN BUFFER
         BIF,S7S9 LOGPRIM1          BRANCH IF NOT X560
*
*        CPU TYPE IS XEROX 560
*
         LI,R2    3
LOGPRIM0 EQU      %
         LB,R7    POLLTYPS,R2       GET A UNIT ADDRESS
         SLS,R7   8                 SHIFT INTO PLACE
         RD,R6    X'10'             READ THE CLUSTER ADDRESS
         SLS,R6   3                 SHIFT CA INTO BITS 18-19-20
         OR,R7    R6                INSERT CA INTO R7
         POLR,R6  0,R7              POLL THAT PROCESSOR
         STH,R6   POLLBUF,R2        STORE INTO ERROR LOG BUFFER
         BDR,R2   LOGPRIM0          FINISH UP..
LOGPRIM1 EQU      %
         LOAD,R2  SX:SPP,R1         * GET PRIVATE PAGE PAGE ADDRESS
         SLS,R2   9                 * AND SHIFT IT TO A WORD ADDRESS
         AND,R0   X1FF              * STRIP NONSENSE FROM F:ELOGB
         AW,R0    R2                * AND ADD THE DISPLACEMENT
         STW,R0   F:EADDR,R1        SAVE FOR MASTER CPU
         B        *R15              RETURN
*
*        FOLLOWING TABLE CONTAINS 560 PROCESSOR UNIT ADDRESSES
*
POLLTYPS DATA,1   0,;               UN-USED
                  5,;               BP UNIT ADDRESS
                  6,;               MI UNIT ADDRESS
                  7                 PI UNIT ADDRESS
         BOUND    4
*
*
*
*
ETYPE    DATA,2   X'2E0B',X'2D0B',X'2F0B',X'2D0B'  T46,T4C,T4D,SIG7 I56
         BOUND    4
X1FF     DATA     X'000001FF'       * MASK WORD (9 BITS)
         PAGE
*F*      NAME:    BEGSOFF
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO PROVIDE AN IN CORE WAIT LOOP FOR SLAVE
*F*               CPUS TO EXECUTE WHILE AWAITING A
*F*               POWER ON INTERRUPT/TRAP.
         PAGE
************************************************************
*                                                          *
*        POWER OFF WAIT LOOP                               *
*                                                          *
************************************************************
BEGSOFF  EQU      %
         MTW,1    OFFCNTER          COUNT THE POWER OFFS
         WAIT
         B        %-1
         PAGE
*F*      NAME:    BEGSON
         SPACE    1
*F*      PURPOSE:
         SPACE    1
*F*               TO PERFORM THE SPECIFIC SLAVE CPU FUNCTIONS IN
*F*               A POWER ON SITUATION
         SPACE    3
*D*      NAME:    BEGSON
         SPACE    1
*D*      REGISTERS:
         SPACE    1
*D*               R8 = CPU HARDWARE ADDRESS UPON ENTRY
*D*               ALL REGISTERS ARE VOLATILE
         SPACE    1
*D*      CALL:
         SPACE    1
*D*               FROM BEGINON IN PFSR AFTER DECIDING CPU IS NOT MASTER
         SPACE    1
*D*      ENVIRONMENT:
         SPACE    1
*D*               ENTERS UNMAPPED,INHIBITS ON,POWERON INTERRUPT HIGH
*D*               GOES MAPPED AND CLEARS INTERRUPT
         SPACE    1
*D*      INTERFACE:
         SPACE    1
*D*               T:PFRET - TO REINITIALIZE SLAVE MAP,LOCKS,ACCESS
*D*               PFSCR - TO INVOKE SLAVE SCREECH IF NO ENVIRON PRESENT
         SPACE    1
*D*      INPUT:
         SPACE    1
*D*               R8 = CPU HARDWARE ADDRESS
*D*               S:ADR = CPU HARDWARE ADDRESS TABLE
*D*               SX:SPP = PHYSICAL PAGE # OF PRIVATE PAGE
*D*               BALANCE = ENVIRON PRESENT FLAG
*D*               OFFCNTER = COUNT OF POWER OFF INTERRUPTS
*D*               ONCNTER = COUNT OF POWERON INTERRUPTS
*D*               NFRST = FLAG FOR MULTIPLE POWEROFFS
*D*               SREGS = REG BLOCK 0
*D*               SREGS1 = REG BLOCK 1
*D*               POWROFF = PSD AT TIME OF POWEROFF
         SPACE    1
*D*      OUTPUT:
         SPACE    1
*D*               BOTH REGISTER BLOCKS RESTORED
*D*               OFFCNTER = 0
*D*               ONCNTER = 0
*D*               BALANCE = 0
*D*               NFRST = 1
         SPACE    1
*D*      DESCRIPTION:
         SPACE    1
*D*               UPON ENTRY FROM BEGINON IN PFSR R8 CONTAINS
*D*               THE HARDWARE ADDRESS OF THE CPU.
*D*               THE PROCESSOR INDEX OF THE GIVEN CPU IS DETERMINED BY
*D*               SEARCHING S:ADR FOR A MATCH IF NOT FOUND EXIT
*D*               IS MADE TO SLVWAIT.  OTHERWISE THE PHYSICAL
*D*               PAGE # OF THE PRIVATE PAGE IS OBTAINED (IF ZERO
*D*               THEN EXIT IS TO SLVWAIT) AND A CALL MADE TO T:PFRET
*D*               TO RELOAD THE MAP, WRITE LOCKS AND ACCESS PROTECT
*D*               UPON RETURN THE BALANCE FLAG IS CHECKED TO INSURE
*D*               THAT A POWEROFF ENVIRONMENT IS PRESENT
*D*               IF NOT EXIT IS MADE TO PFSCR TO INVOKE A SCREECH
*D*               OTHERWISE BOTH REGISTER BLOCKS ARE RESTORED
*D*               THE VARIOUS COUNTERS ARE RESET AND EXECUTION
*D*               RESUMES AT THE POINT OF THE POWEROFF INTERRUPT/TRAP
         PAGE
************************************************************
*                                                          *
*        SLAVE FUNCTIONS FOR POWER ON                      *
*                                                          *
************************************************************
BEGSON   EQU      %
         LI,R1    NSCPU
         CW,R8    S:ADR,R1          IS IT I
         BE       BSON1             YEP
         BDR,R1   %-2               CHECK NEXT
         BAL,R11  SLVWAIT           I'M NOT HERE, BAILOUT
BSON1    EQU      %
         LOAD,R8  SX:SPP,R1         GET PHYSICAL PAGE #
         BNEZ     %+2               OK
         BAL,R11  SLVWAIT           BAD NEWS,BAILOUT
         BAL,R12  T:PFRET           RELOAD MAP,LOCKS,ACCESS
         MTW,1    ONCNTER           COUNT POWER ON
         MTW,0    BALANCE           ANY ENVIRON PRESENT
         BEZ      PFSCR             NO, GO SCREECH
         LPSD,1   DEPSD             CLEAR POWERON INTERRUPT
CLEAR    EQU      %
         LM,R0    SREGS             RESTORE REG BLOCK 0
         LRP      RP1               POINT TO RP1
         LM,R0    SREGS1            RESTORE REG BLOCK 1
         LI,R0    0
         STW,R0   OFFCNTER          ZERO OUT COUNTERS
         STW,R0   ONCNTER
         STW,R0   BALANCE
         LI,R0    1
         STW,R0   NFRST             RESTORE MULTIPLE POWEROFF FLAG
         LW,R0    SREGS
         LPSD,8   POWROFF           RTN TO POINT OF POWEROFF
         END

