         PCC      0
         TITLE    'T R A P    R E C E I V E R S'
***************************************************************
*                                                             =
*                       T C A T C H                           *
*                                                             *
*        THIS MODULE CONTAINS TRAP AND INTERRUPT              *
*        CATCHERS AND OTHER DATA CELLS WHICH WILL             *
*        BE MAPPED ONTO DIFFERENT PAGES FOR EACH              *
*        CPU.  THE MASTER CPU WILL BE MAPPED ONE-             *
*        TO-ONE .                                             *
*                                                             *
*        ANY FUTURE DATA CELLS WHICH  SHOULD BE LOCAL         *
*        TO A CPU SHOULD BE LOCATED IN THIS MODULE.           *
*                                                             *
*        THIS MODULE IS LOADED WITH THE MONITOR ROOT          *
*        AND WITH MOOSE, THE MULTIPROCESSING OPERATIONS       *
*        GHOST, WHICH WILL SET UP THE PRIVATE DATA FOR        *
*        EACH SLAVE PROCESSOR.                                *
*                                                             *
***************************************************************
         SPACE    3
*        THE ASSEMBLY SWITCH 'MASTER' SHOULD BE SET TO
*        ONE TO GENERATE TCATCH FOR THE MASTER CPU(ROOT VERSION)
*        AND SET TO ZERO TO GENERATE THE SLAVE CPU TCATCH (MOOSE VERSION).
*
MASTER   SET      1
         OPEN     XPSD,B            PREVENT DBL DEF COM
         PAGE
***************************************************************
*                        D E F S                              *
***************************************************************
         SPACE    3
*        MOST DEFS ARE GENERATED BY THE PROCS:
*                                              DATUM
*                                              EQ
*                                              :PSD
*
         DO       MASTER
         DEF      XPSD46
         DEF      BLOCKER           SLAVE CPU BLOCK ROUTINE
         FIN
         PAGE
***************************************************************
*                                                             *
*                       R E F S                               *
*                                                             *
***************************************************************
         SPACE    3
*        MOST REFS ARE ALSO PROC GENERATED
*
         SPACE    1
         REF      J:OVHTIM
         DO       MASTER
         SREF     COCFLAG           COC PRESENT FLAG
         FIN
         PAGE
*
*        PROC TO GENERATE DATA ITEMS
*
         SPACE    1
DATUM    CNAME
         PROC
         DO       NUM(CF)=2
LF       DATA,CF(2) AF
         ELSE
LF       DATA     AF
         FIN
         DEF      LF
         PEND
         SPACE    3
*
*        PROC TO GENERATE LABELS
*
EQ       CNAME
         PROC
LF       RES      0
         DEF      LF
         PEND
         DEF      TCATCH:           PATCHING DEF
TCATCH:  RES
         SPACE    2
XPSD     CNAME    X'0F'
B        CNAME    X'68'
         PROC
LF       GEN,1,7,4,3,17 AFA,NAME,CF(2),AF(2),AF(1)
         PEND
         PAGE
*
*        PROC TO GENERATE PSDS
*
         SPACE    1
:PSD     CNAME
         PROC
         LOCAL    :B9MA,:560MA
         DO1      TCOR(S:FR,:B9)
         REF      :B9,:B560
         BOUND    8
P        SET      S:KEYS(2,*0,CC,IA,WK,RP,18,OMA,RES,;
                  FR,FS,FZ,FN,(SLAVE,MASTER),MAP,DM,AM,;
                  CI,II,EI,INH)
         DO       (P(2)&X'2040')=0  NOT MAP & NOT OMA
:B9MA    SET      :B9               SET FOR BIG9'S ONLY
:B560MA  SET      :B560             SET FOR BIG560'S ONLY
         ELSE
:B9MA    SET      0
:B560MA  SET      0
         FIN
         DO1      TCOR(AF(P(4),2),S:FR)  REF IA IF NOT DEFINED
         SREF     AF(P(4),2)        IA
LF       GEN,((P(2)&X'1000')>0)*64,;   OPTIONAL TWO WORDS OF ZEROS
         4,8,3,17,;   CC,(FR,FS,FZ,FN,SLAVE,MAP,DM,AM),,IA
         2,2,1,3,1,6,1,;            0,WK,,(CI,II,EI),:B9MA,,:B9MA
         8,4,1,1,2 ;                0,RP,,:B560MA,0
         0,;                        OPTIONAL TWO WORDS OF ZEROS
         AF(P(3),2),;               CC
         (P(2)**-4)&X'FF',;         FR,FS,FZ,FN,SLAVE,MAP,DM,AM
         0,;
         AF(P(4),2),;               IA
         0,;
         AF(P(5),2),;               WK
         0,;
         ((P(2)**-1)&7)|((P(2)&1)*7),;  CI,II,EI, OR INH
         :B9MA,;                    MA FOR SIGMA 9
         0,;
         :B9MA,;                    EA FOR SIGMA 9
         0,;
         AF(P(6),2),;               RP
         0,;
         :B560MA,;                  MA FOR XEROX 560
         0
         DEF      LF
         PEND
         PAGE
*
*        REGISTER DEFINITIONS
*
R1       EQU      1
         PAGE
***************************************************************
*                                                             *
*                 X P S D    T A R G E T S                    *
*                                                             *
***************************************************************
         SPACE    3
         DO       MASTER
TPSDBASE EQ
         ELSE
MOOSD    EQ
         FIN
NOPPSD   :PSD     RES,(IA,NOPPGM),(WK,1),INH,MAP
UNIMPPSD :PSD     RES,(IA,UNIMP),(WK,1),INH,MAP
STKLPSD  :PSD     RES,(IA,STKOVF),(WK,1),INH,MAP
FIXOVPSD :PSD     RES,(IA,FIXOVF),(WK,1),INH,MAP
FLTFPSD  :PSD     RES,(IA,FLTFLT),(WK,1),INH,MAP
DECFPSD  :PSD     RES,(IA,DECFLT),(WK,1),INH,MAP
CAL1PSD  :PSD     RES,(IA,CAL1P),(WK,1),INH,MAP
CAL2PSD  :PSD     RES,(IA,CAL2XXX),(WK,1),INH,MAP
CAL3PSD  :PSD     RES,(IA,CAL3XXX),(WK,1),INH,MAP
CAL4PSD  :PSD     RES,(IA,CAL4XXX),(WK,1),INH,MAP
         DO       MASTER
CLK4PSD  :PSD     RES,(IA,CLK4),(WK,1),INH
         ELSE
CLK4PSD  :PSD     RES,(IA,T:SQECK),(WK,1),MAP
         FIN
         SPACE    1
*        TRAP X'47' - INTERPROCESSOR TRAP
         SPACE    1
IPT47    :PSD     RES,(IA,IPT),(WK,1),INH
         PAGE
*
*        FAULT HANDLING PSDS
*
         SPACE    2
*    THE FOLLOWING PSDS ARE ORDER DEPENDENT
         SPACE    1
*        TRAP X'46' - WATCHDOG TIMER RUNOUT
         SPACE    1
         DO       MASTER
PSD%T46  :PSD     (IA,CSE%ERR),RES,INH
         ELSE
PSD%T46  :PSD     (IA,T46ERR),RES,INH,MAP
         FIN
         DO       MASTER
PSD%T4C  :PSD     (IA,CSE%ERR),RES,INH,FN
         ELSE
PSD%T4C  :PSD     (IA,T4CERR),RES,INH,MAP,FN
         FIN
         DO       MASTER
PSD%T4D  :PSD     (IA,CSE%ERR),RES,INH,FZ
         ELSE
PSD%T4D  :PSD     (IA,T4DERR),RES,INH,MAP,FZ
         FIN
PSD%I56  :PSD     (IA,CSE%I56),RES,INH,FN,FZ
*    END OF ORDER DEPENDENT PSDS
PSD%I57  :PSD     (IA,CSE%I57),RES,INH
         DO       MASTER
PFSR46PSD EQ
         FIN
         :PSD     RES,(IA,PFSR46),INH
CTRAPSD  :PSD     (IA,T:CTRAPM),MAP,RES,INH,(WK,1)
         DO       MASTER
POWROFF  :PSD     (IA,BEGINOFF),RES,INH,(RP,COCFLAG)
         ELSE
POWROFF  :PSD     (IA,BEGINOFF),RES,INH,MAP,(RP,1)
         FIN
         DO       MASTER
RCVPSD   :PSD     (IA,RECOVER0),RES,INH,(RP,COCFLAG)  PSD TO ENTER RECOVERY
         ELSE
RCVPSD   :PSD     (IA,T:SCREECHS),RES,INH,MAP   PSD TO ENTER SLAVE PROCESSING
         FIN
         PAGE
*
*        SLAVE CPU BLOCK PSD
*
         DO       MASTER=0
         :PSD     (IA,T:BLOCK),(WK,1),RES,MAP
         ELSE
BLKPSD   :PSD     (IA,T:BLOCK),(WK,1),RES,MAP
         FIN
*
*
*        PATCH SPACE
*
MTEMP:   DATUM    0,0,0,0,0,0,0,0
         PAGE
***************************************************************
*                                                             *
*                 D A T A    C E L L S                        *
*                                                             *
***************************************************************
         SPACE    3
         BOUND    8
PULLE1   DATUM    0,0               TEMP STORAGE FOR PULLE
S:INTBIT DATUM    0,0               WRITE DIRECT,GROUP
S:CLOCK4 DATUM    J:OVHTIM          DIRECTOR FOR CLOCK 4 ACCOUNTING
S:CUN    DATUM    0                 CURRENT USER NUMBER
         BOUND    8
S:DT     DATUM    0                 SAVE SPACE FOR DELTAT
S:IDT    DATUM    0                 SAVE SPACE FOR IDELTAT
S:PNO    DATUM    0                 PROCESSOR NUMBER
TEMP%BREG DATUM   0                 TEMP FOR ENTRY TO SAVE BRANCH REG(560)
         BOUND    8
TEMP     DATUM    0                 TEMP
TEMP1    DATUM    0                    *
TEMP2    DATUM    0                    CELLS
         DO       MASTER=0
         REF      PFSR46PSD
         FIN
XPSD46   XPSD,0   PFSR46PSD         INTERCEPT TRAP 46
C:CAL    DATUM    0                 COUNT OF #CALS
PFSRSW   DATUM    0                 SENSE SWITCH SETTINGS FOR 560
BALANCE  DATUM    0                 FOR POWON AND POWROFF
OFFCNTER DATUM    0                 POWER OFF INT. COUNTER
ONCNTER  DATUM    0                 POWER ON INT. COUNTER
NFRST    DATUM    1                 CELL FOR MULTIPOWEROFFS
SREGS    EQ                         REGISTER BLOCK ZERO SAVE FOR PFSR
         DO1      16
         DATA     0
         BOUND    8
F:STBL   EQ                         START OF SLAVE FAULT TABLE AREA
FD:PSD   DATUM    0,0               PSD AT TIME OF SLAVE FAULT
SREGS1   EQ                         REG BLOCK ONE FOR PFSR ALSO
F:REGS   EQ                         REGS AT TIME OF FAULT
         DO1      16
         DATA     0
FB:CF    DATUM    0                 CCS & FLOAT CONTROLS AT FAULT TIME
FB:END   DATUM    0                 END ACTION DRIVER
         BOUND    8
F:ELOGB  DATUM    0,0               ERRLOG ENTRY BUFFER FOR SLAVE FAULT
*                                   CODE,TIME WORDS
FD:EPSD  DATUM    0,0               PSD ENTRY WORDS
         DATA     0,0               RESERVED
F:IREAL  DATUM    0                 REAL ADDR OF TRAP INST
F:INST   DATUM    0                 TRAPPED INSTRUCTION
F:EVIRT  DATUM    0                 ANLZ CC AND VIRTUAL ADDR
F:EREAL  DATUM    0                 REAL EFFECTIVE ADDR
FH:IFLG  DATUM    0                 CCS AND FLAGS IN LEFT HALF WORD
*
F:BREG   DATUM    0                 X560 LAST BRANCH REGISTER
F:TEMP1  DATUM    0                 TEMP CELL FOR FAULT HANDLING
F:TEMP2  DATUM    0                 TEMP CELL FOR FAULT HANDLING
         PAGE
*D*      BLOCK SUBROUTINE
*D*      THIS ROUTINE IS CONTAINED IN A VIRTUAL PAGE MAPPED
*D*      DIFFERENTLY ON MASTER AND SLAVE CPUS.  THE MASTER
*D*      VERSION SIMPLY DOES A RETURN BRANCH WHILE THE SLAVE
*D*      VERSION WILL CALL T:BLOCK CAUSING THE SLAVE CPU TO
*D*      DISCONTINUE PROCESSING OF ITS CURRENT USER.
*D*
*D*      LINK: R1
*D*
BLOCKER  EQU      %
         DO       MASTER
         B        0,R1              RETURN IF MASTER
         ELSE
         REF      BLKPSD
         XPSD,10  BLKPSD            BLOCK IF SLAVE
         FIN      MASTER
         DO       MASTER=0
MOOSDSZ  EQU      %-MOOSD
         DEF      MOOSDSZ
         ELSE
TCATEND  EQ
         FIN
         CLOSE    XPSD,B
         END

