/* $Header:8530.h 12.0$ */
/* $ACIS:8530.h 12.0$ */
/* $Source: /ibm/acis/usr/sys/standca/RCS/8530.h,v $ */

#if !defined(lint) && !defined(LOCORE)  && defined(RCS_HDRS)
static char *rcsid8530 = "$Header:8530.h 12.0$";
#endif

/*
 * 5799-WZQ (C) COPYRIGHT IBM CORPORATION 1986
 * LICENSED MATERIALS - PROPERTY OF IBM
 * REFER TO COPYRIGHT INSTRUCTIONS FORM NUMBER G120-2083
 */
/* Support for the Zilog 8530                                         */

#define    Pri8530       0xF000202A    /* First 8530 addr. */
#define    Alt8530       0xF000002A    /* Second 8530 addr. */
#define    Shr8530       0xF000042A    /* Shared 8530 data */
#define    Rst8530       0xF000002D    /* Reset 8530 addr. */
#define    RstRS232      0xF000042D    /* Reset RS232 addr. */

#define    Chn8530A      0	       /* DMA channel for A */
#define    Chn8530B      1	       /* DMA channel for B */

#define    Dma8530B      0x80	       /* Enable DMA       */
#define    Irq8530B      0x20	       /* Interrupt ack.   */
#define    Dtr8530B      0x10	       /* Set DTR          */
#define    Dma8530A      0x08	       /* Enable DMA       */
#define    Irq8530A      0x02	       /* Interrupt Ack.   */
#define    Dtr8530A      0x01	       /* Set DTR          */

#define    RgI8530B      0x40	       /* Ring indicate    */
#define    Dsr8530B      0x20	       /* Data Set Ready   */
#define    Fbk8530B      0x10	       /* DTR feedback     */
#define    RgI8530A      0x04	       /* Ring indicate    */
#define    Dsr8530A      0x02	       /* Data Set Ready   */
#define    Fbk8530A      0x01	       /* DTR feedback     */
